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e70fec871b
defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit
296 lines
4.8 KiB
C
296 lines
4.8 KiB
C
/* ------------------------------------------------------------------ */
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/* WARNING: relative order of tokens is important. */
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/*
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* The specifications are available under https://riscv.org/technical/specifications/
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*/
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/* register */
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DEF_ASM(x0)
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DEF_ASM(x1)
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DEF_ASM(x2)
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DEF_ASM(x3)
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DEF_ASM(x4)
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DEF_ASM(x5)
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DEF_ASM(x6)
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DEF_ASM(x7)
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DEF_ASM(x8)
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DEF_ASM(x9)
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DEF_ASM(x10)
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DEF_ASM(x11)
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DEF_ASM(x12)
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DEF_ASM(x13)
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DEF_ASM(x14)
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DEF_ASM(x15)
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DEF_ASM(x16)
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DEF_ASM(x17)
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DEF_ASM(x18)
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DEF_ASM(x19)
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DEF_ASM(x20)
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DEF_ASM(x21)
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DEF_ASM(x22)
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DEF_ASM(x23)
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DEF_ASM(x24)
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DEF_ASM(x25)
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DEF_ASM(x26)
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DEF_ASM(x27)
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DEF_ASM(x28)
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DEF_ASM(x29)
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DEF_ASM(x30)
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DEF_ASM(x31)
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/* register macros */
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DEF_ASM(zero)
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DEF_ASM(ra)
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DEF_ASM(sp)
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DEF_ASM(gp)
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DEF_ASM(tp)
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DEF_ASM(t0)
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DEF_ASM(t1)
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DEF_ASM(t2)
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DEF_ASM(fp)
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DEF_ASM(s1)
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DEF_ASM(a0)
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DEF_ASM(a1)
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DEF_ASM(a2)
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DEF_ASM(a3)
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DEF_ASM(a4)
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DEF_ASM(a5)
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DEF_ASM(a6)
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DEF_ASM(a7)
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DEF_ASM(s2)
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DEF_ASM(s3)
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DEF_ASM(s4)
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DEF_ASM(s5)
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DEF_ASM(s6)
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DEF_ASM(s7)
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DEF_ASM(s8)
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DEF_ASM(s9)
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DEF_ASM(s10)
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DEF_ASM(s11)
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DEF_ASM(t3)
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DEF_ASM(t4)
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DEF_ASM(t5)
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DEF_ASM(t6)
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DEF_ASM(s0) // = x8
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DEF_ASM(pc)
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#define DEF_ASM_WITH_SUFFIX(x, y) \
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DEF(TOK_ASM_ ## x ## _ ## y, #x #y)
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/* Loads */
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DEF_ASM(lb)
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DEF_ASM(lh)
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DEF_ASM(lw)
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DEF_ASM(lbu)
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DEF_ASM(lhu)
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/* RV64 */
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DEF_ASM(ld)
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DEF_ASM(lwu)
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/* Stores */
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DEF_ASM(sb)
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DEF_ASM(sh)
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DEF_ASM(sw)
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/* RV64 */
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DEF_ASM(sd)
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/* Shifts */
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DEF_ASM(sll)
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DEF_ASM(srl)
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DEF_ASM(sra)
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/* RV64 */
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DEF_ASM(slli)
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DEF_ASM(srli)
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DEF_ASM(sllw)
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DEF_ASM(slld)
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DEF_ASM(slliw)
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DEF_ASM(sllid)
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DEF_ASM(srlw)
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DEF_ASM(srld)
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DEF_ASM(srliw)
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DEF_ASM(srlid)
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DEF_ASM(srai)
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DEF_ASM(sraw)
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DEF_ASM(srad)
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DEF_ASM(sraiw)
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DEF_ASM(sraid)
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/* Arithmetic */
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DEF_ASM(add)
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DEF_ASM(addi)
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DEF_ASM(sub)
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DEF_ASM(lui)
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DEF_ASM(auipc)
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/* RV64 */
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DEF_ASM(addw)
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DEF_ASM(addiw)
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DEF_ASM(subw)
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/* Logical */
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DEF_ASM(xor)
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DEF_ASM(xori)
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DEF_ASM(or)
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DEF_ASM(ori)
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DEF_ASM(and)
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DEF_ASM(andi)
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/* Compare */
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DEF_ASM(slt)
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DEF_ASM(slti)
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DEF_ASM(sltu)
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DEF_ASM(sltiu)
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/* Branch */
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DEF_ASM(beq)
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DEF_ASM(bne)
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DEF_ASM(blt)
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DEF_ASM(bge)
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DEF_ASM(bltu)
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DEF_ASM(bgeu)
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/* Jump */
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DEF_ASM(jal)
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DEF_ASM(jalr)
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/* Sync */
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DEF_ASM(fence)
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/* Zifencei extension */
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DEF_ASM_WITH_SUFFIX(fence, i)
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/* System call */
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/* used to be called scall and sbreak */
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DEF_ASM(ecall)
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DEF_ASM(ebreak)
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/* Counters */
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DEF_ASM(rdcycle)
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DEF_ASM(rdcycleh)
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DEF_ASM(rdtime)
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DEF_ASM(rdtimeh)
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DEF_ASM(rdinstret)
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DEF_ASM(rdinstreth)
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/* no operation */
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DEF_ASM(nop)
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DEF_ASM_WITH_SUFFIX(c, nop)
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/* “M” Standard Extension for Integer Multiplication and Division, V2.0 */
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DEF_ASM(mul)
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DEF_ASM(mulh)
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DEF_ASM(mulhsu)
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DEF_ASM(mulhu)
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DEF_ASM(div)
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DEF_ASM(divu)
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DEF_ASM(rem)
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DEF_ASM(remu)
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/* RV64 */
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DEF_ASM(mulw)
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DEF_ASM(divw)
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DEF_ASM(divuw)
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DEF_ASM(remw)
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DEF_ASM(remuw)
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/* "C" Extension for Compressed Instructions, V2.0 */
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/* Loads */
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DEF_ASM_WITH_SUFFIX(c, li)
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DEF_ASM_WITH_SUFFIX(c, lw)
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DEF_ASM_WITH_SUFFIX(c, lwsp)
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/* single float */
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DEF_ASM_WITH_SUFFIX(c, flw)
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DEF_ASM_WITH_SUFFIX(c, flwsp)
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/* double float */
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DEF_ASM_WITH_SUFFIX(c, fld)
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DEF_ASM_WITH_SUFFIX(c, fldsp)
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/* RV64 */
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DEF_ASM_WITH_SUFFIX(c, ld)
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DEF_ASM_WITH_SUFFIX(c, ldsp)
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/* Stores */
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DEF_ASM_WITH_SUFFIX(c, sw)
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DEF_ASM_WITH_SUFFIX(c, sd)
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DEF_ASM_WITH_SUFFIX(c, swsp)
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DEF_ASM_WITH_SUFFIX(c, sdsp)
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/* single float */
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DEF_ASM_WITH_SUFFIX(c, fsw)
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DEF_ASM_WITH_SUFFIX(c, fswsp)
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/* double float */
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DEF_ASM_WITH_SUFFIX(c, fsd)
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DEF_ASM_WITH_SUFFIX(c, fsdsp)
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/* Shifts */
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DEF_ASM_WITH_SUFFIX(c, slli)
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DEF_ASM_WITH_SUFFIX(c, slli64)
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DEF_ASM_WITH_SUFFIX(c, srli)
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DEF_ASM_WITH_SUFFIX(c, srli64)
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DEF_ASM_WITH_SUFFIX(c, srai)
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DEF_ASM_WITH_SUFFIX(c, srai64)
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/* Arithmetic */
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DEF_ASM_WITH_SUFFIX(c, add)
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DEF_ASM_WITH_SUFFIX(c, addi)
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DEF_ASM_WITH_SUFFIX(c, addi16sp)
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DEF_ASM_WITH_SUFFIX(c, addi4spn)
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DEF_ASM_WITH_SUFFIX(c, lui)
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DEF_ASM_WITH_SUFFIX(c, sub)
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DEF_ASM_WITH_SUFFIX(c, mv)
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/* RV64 */
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DEF_ASM_WITH_SUFFIX(c, addw)
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DEF_ASM_WITH_SUFFIX(c, addiw)
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DEF_ASM_WITH_SUFFIX(c, subw)
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/* Logical */
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DEF_ASM_WITH_SUFFIX(c, xor)
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DEF_ASM_WITH_SUFFIX(c, or)
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DEF_ASM_WITH_SUFFIX(c, and)
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DEF_ASM_WITH_SUFFIX(c, andi)
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/* Branch */
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DEF_ASM_WITH_SUFFIX(c, beqz)
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DEF_ASM_WITH_SUFFIX(c, bnez)
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/* Jump */
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DEF_ASM_WITH_SUFFIX(c, j)
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DEF_ASM_WITH_SUFFIX(c, jr)
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DEF_ASM_WITH_SUFFIX(c, jal)
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DEF_ASM_WITH_SUFFIX(c, jalr)
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/* System call */
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DEF_ASM_WITH_SUFFIX(c, ebreak)
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/* XXX F Extension: Single-Precision Floating Point */
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/* XXX D Extension: Double-Precision Floating Point */
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/* from the spec: Tables 16.5–16.7 list the RVC instructions. */
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/* “Zicsr”, Control and Status Register (CSR) Instructions, V2.0 */
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DEF_ASM(csrrw)
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DEF_ASM(csrrs)
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DEF_ASM(csrrc)
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DEF_ASM(csrrwi)
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DEF_ASM(csrrsi)
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DEF_ASM(csrrci)
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/* Privileged Instructions */
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DEF_ASM(mrts)
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DEF_ASM(mrth)
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DEF_ASM(hrts)
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DEF_ASM(wfi)
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