55 Commits

Author	SHA1	Message	Date
Michael Matz	b1c7520886	riscv: more insns ... * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.	2019-09-01 23:13:18 +02:00
Michael Matz	16edda58b7	riscv: Add more ops and fixes ... * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.	2019-09-01 23:13:08 +02:00
Michael Matz	ef7c1a4e96	riscv: Implement some loads and calls ... so that a hello world works.	2019-08-14 18:22:18 +02:00
Michael Matz	35d7b5934e	riscv: hacky prolog, epilog and return ... this now allows to compile a simple working example: int main(void) { return 0; }	2019-08-14 18:22:14 +02:00
Michael Matz	0676d5bc23	riscv64: Add skeleton target	2019-08-14 18:18:46 +02:00