67 Commits

Author	SHA1	Message	Date
Michael Matz	ddb0c2de92	riscv: support large stack and far jumps ... for 101_cleanup we need 256kb stack (with the associated problem of needing a larger prologue/epilogue) as well as jumps out of range for the 21bit offsets (exactly for second part of the prologue).	2019-09-01 23:13:19 +02:00
Michael Matz	b69c2ea2cf	riscv: fix 90_struct-init ... indirect calls were broken.	2019-09-01 23:13:19 +02:00
Michael Matz	31ecaa7c28	riscv: GOT loads, signed remainder, ELF flags ... * support loading sym addresses from GOT: important for weak syms, fixes 104_inline. This is still incomplete, it only works for taking the sym address, not for directly loading/storing into such symbols (i.e. not for VT_LVAL) * another op: '%' * ELF flags: add EF_RISCV_FLOAT_ABI_DOUBLE, which is our ABI.	2019-09-01 23:13:19 +02:00
Michael Matz	5390a729d9	riscv: Implement VLA stuff ... makes 78_vla_label and 79_vla_continue work.	2019-09-01 23:13:19 +02:00
Michael Matz	9164594d1f	riscv: load 64bit constants, and 32bit shifts ... fixes 95_bitfields. loading 64bit constants is suboptimal right now. int32_t shifts really need to use the W form, otherwise 'x << 24 >> 24' doesn't extract the low 8 bits.	2019-09-01 23:13:19 +02:00
Michael Matz	215bc1aab4	riscv: Add sar, shr insn ... fixes 92_enum_bitfield.	2019-09-01 23:13:19 +02:00
Michael Matz	f64d460d29	riscv: fix 72_long_long_constant ... 32bit signed constants larger than 0x7ffff800 were handled wrongly.	2019-09-01 23:13:19 +02:00
Michael Matz	9309585dbe	riscv: some long double support ... long double on risc-v is 128bit, but there are no registers for that type (without the Q ISA extension). They are passed like two 64bit integers values (with an exception for varargs, where it's an aligned register pair). This all requires some hacks in generic code as otherwise RC_FLOAT regs are tried for holding values of long double type, but we need a RC_INT register pair. This really could all use some cleanup for all archs. This doesn't implement any conversions of operations for long double, but it's enough to get 70_floating_point_literals working.	2019-09-01 23:13:19 +02:00
Michael Matz	9c1b17407f	riscv: Make 32_leds work ... * more ops: umod and udiv * large immediates: suboptimal code, e.g. when loading 0xffffffffU (which is what a cast from long to int does). tests2 work up to 67_macro_concat.	2019-09-01 23:13:19 +02:00
Michael Matz	02c8e69a07	riscv: fp parameters ... makes 23_type_coercion work. (clean up to 31_args)	2019-09-01 23:13:19 +02:00
Michael Matz	0d3db83f16	riscv: float ops ... * compares * add/sub/mul/div * float-float converts makes 22_floating_point work.	2019-09-01 23:13:19 +02:00
Michael Matz	9214087259	riscv: More insns, operands and arg slots ... * load/store of FP ops * load/store from symbols, VT_LLOCAL, some with large addend * load of VT_JMP result * calls with many args (stack slots) * calls with FP args * more operations: and/or/xor/div	2019-09-01 23:13:19 +02:00
Michael Matz	b1c7520886	riscv: more insns ... * register indirect loads and stores * load of local addresses * indirect calls (uses ra as temporary reg if necessary) * operations *, -, << * gen_cvt_sxtw: is not needed in most cases, let's see tests2 runs until (incl) 09_do_while.	2019-09-01 23:13:18 +02:00
Michael Matz	16edda58b7	riscv: Add more ops and fixes ... * implement compares, gtst and gsym/gjmp and add * implement stores (simple cases) * fix arg passing with more than one register arg, fix loads to not always use 8byte loads * add some predefined macros: __riscv, __riscv_xlen, __SIZEOF_POINTER__ (needed by glibc header) The first 5 tests of tests2 run now.	2019-09-01 23:13:08 +02:00
Michael Matz	ef7c1a4e96	riscv: Implement some loads and calls ... so that a hello world works.	2019-08-14 18:22:18 +02:00
Michael Matz	35d7b5934e	riscv: hacky prolog, epilog and return ... this now allows to compile a simple working example: int main(void) { return 0; }	2019-08-14 18:22:14 +02:00
Michael Matz	0676d5bc23	riscv64: Add skeleton target	2019-08-14 18:18:46 +02:00