9 Commits

Author	SHA1	Message	Date
noneofyourbusiness	e70fec871b	riscv64-tok.h: update with more instructions from the spec ... defined tokens for C, M, Ziscr extensions. separate the base RV32 instructions from the RV64, for potential future re-use in a RV32-only assembler, from which the RV64-tok can #include scall, sbreak have been renamed (page 7 of spec), necessitating some renaming in riscv64-asm.c riscv-spec-20191213.pdf was used, in which the "V" extension is not yet ratified. available under https://riscv.org/technical/specifications/ Tables 16.5–16.7 do not list any "scall" neither does the privileged spec 3 additional tokens not present in the tables were removed note that this riscv64-asm.c still contains defects, which will be addressed in another commit	2023-08-10 14:25:03 +02:00
herman ten brugge	cd627c6c40	Fix riscv assembler ... riscv64-asm.c: asm_opcode: add return asm_parse_regvar: add abi register names riscv64-tok.h: add abi register names	2022-06-07 20:53:14 +02:00
Danny Milosavljevic	b28bf50d2b	riscv64-asm: Add beq, bne, blt, bge, bltu, bgeu	2021-04-23 20:23:45 +02:00
Danny Milosavljevic	9c0760a4d4	riscv64-asm: Add lb, lh, lw, lbu, lhu, ld, lwu, sb, sh, sw, sd	2021-04-23 20:23:45 +02:00
Danny Milosavljevic	1e37ec4917	riscv64-asm: Add add, addi, sub, addw, addd, addiw, addid, subw, subd, xor, xori, or, ori, and, andi, slt, slti, sltu, sltiu	2021-04-23 20:23:45 +02:00
Danny Milosavljevic	8b1a89fbdf	riscv64-asm: Add sll, slli, srl, srli, sra, srai, sllw, slld, slliw, sllid, srlw, srld, srliw, srlid, sraw, srad, sraiw, sraid	2021-04-23 20:23:45 +02:00
Danny Milosavljevic	0b1cc489e1	riscv64-asm: Add lui, auipc	2021-04-23 20:23:45 +02:00
Danny Milosavljevic	e5a898e510	riscv64-asm: Add rdcycle, rdcycleh, rdtime, rdtimeh, rdinstret, rdinstreth	2021-04-23 20:23:45 +02:00
Danny Milosavljevic	4891ab71a0	riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi	2021-04-23 20:23:45 +02:00