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riscv64: fcvt.d.s doesn't need a rounding mode

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it doesn't round so the RM field can be zero.  According to some
sourcs it should be set to zero by software in these cases, and
the binutils disassembler doesn't like us setting it to 7.

This shouldn't matter in practice, but who knows.
This commit is contained in:
Michael Matz 2020-04-16 00:00:13 +02:00
parent 2f94390223
commit fb1fb8219c
1 changed files with 2 additions and 2 deletions
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4
riscv64-gen.c
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@ -1176,9 +1176,9 @@ ST_FUNC void gen_cvt_ftof(int dt)
rs = gv(RC_FLOAT);
rd = get_reg(RC_FLOAT);
if (dt == VT_DOUBLE)
EI(0x53, 7, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (dyn rm)
EI(0x53, 0, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (no rm)
else
EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS
EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS (dyn rm)
vtop->r = rd;
}
}