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Fix atomic test_and_set and clear
The __atomic_test_and_set and __atomic_clear code was correct. They needed locking. Replaced to code with assembly code. The changes are in include/stdatomic.h, lib/stdatomic.c, lib/atomic.S Enabled tests/tests2/124_atomic_counter.c for apple again. Also moved lib/fetch_and_add.S code to lib/atomic.S. Removed lib/fetch_and_add.S Adjusted lib/Makefile
This commit is contained in:
herman ten brugge
parent
c8ef84c854
commit
f89a6f12a7
@ -80,17 +80,12 @@ typedef struct {
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#define ATOMIC_FLAG_INIT {0}
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#define atomic_flag_test_and_set_explicit(object, order) \
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({ bool ret, value = 1; \
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__atomic_exchange(&(object)->value, &value, &ret, order); \
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ret; \
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})
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__atomic_test_and_set((void *)(&((object)->value)), order)
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#define atomic_flag_test_and_set(object) \
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atomic_flag_test_and_set_explicit(object, __ATOMIC_SEQ_CST)
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#define atomic_flag_clear_explicit(object, order) \
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({ bool value = 0; \
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__atomic_store(&(object)->value, &value, order); \
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})
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__atomic_clear((bool *)(&((object)->value)), order)
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#define atomic_flag_clear(object) \
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atomic_flag_clear_explicit(object, __ATOMIC_SEQ_CST)
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10
lib/Makefile
10
lib/Makefile
@ -42,11 +42,11 @@ $(X)BT_O += tcov.o
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DSO_O = dsohandle.o
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I386_O = libtcc1.o alloca.o alloca-bt.o stdatomic.o $(BT_O)
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X86_64_O = libtcc1.o alloca.o alloca-bt.o stdatomic.o $(BT_O)
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ARM_O = libtcc1.o armeabi.o alloca.o armflush.o fetch_and_add.o stdatomic.o atomic.o $(BT_O)
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ARM64_O = lib-arm64.o fetch_and_add.o stdatomic.o atomic.o $(BT_O)
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RISCV64_O = lib-arm64.o fetch_and_add.o stdatomic.o atomic.o $(BT_O)
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I386_O = libtcc1.o alloca.o alloca-bt.o stdatomic.o atomic.o $(BT_O)
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X86_64_O = libtcc1.o alloca.o alloca-bt.o stdatomic.o atomic.o $(BT_O)
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ARM_O = libtcc1.o armeabi.o alloca.o armflush.o stdatomic.o atomic.o $(BT_O)
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ARM64_O = lib-arm64.o stdatomic.o atomic.o $(BT_O)
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RISCV64_O = lib-arm64.o stdatomic.o atomic.o $(BT_O)
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WIN_O = crt1.o crt1w.o wincrt1.o wincrt1w.o dllcrt1.o dllmain.o
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OBJ-i386 = $(I386_O) $(BCHECK_O) $(DSO_O)
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247
lib/atomic.S
247
lib/atomic.S
@ -12,7 +12,49 @@
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# define _(s) s
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#endif
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#if defined __arm__
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#if defined __i386__
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.text
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.align 2
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.global _(__atomic_test_and_set)
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.type _(__atomic_test_and_set), %function
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_(__atomic_test_and_set):
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movl 4(%esp), %edx
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movl $1, %eax
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xchgb (%edx), %al
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ret
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.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
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.global _(__atomic_clear)
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.type _(__atomic_clear), %function
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_(__atomic_clear):
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movl 4(%esp), %edx
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xorl %eax, %eax
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xchgb (%edx), %al
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ret
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.size _(__atomic_clear), .-_(__atomic_clear)
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#elif defined __x86_64__
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.text
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.align 2
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.global _(__atomic_test_and_set)
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.type _(__atomic_test_and_set), %function
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_(__atomic_test_and_set):
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movl $1, %eax
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xchgb (%rdi), %al
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ret
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.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
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.global _(__atomic_clear)
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.type _(__atomic_clear), %function
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_(__atomic_clear):
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xorl %eax, %eax
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xchgb (%rdi), %al
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ret
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.size _(__atomic_clear), .-_(__atomic_clear)
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#elif defined __arm__
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#ifndef __TINYC__
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.arch armv6k
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@ -21,6 +63,91 @@
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.text
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.align 2
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.global _(fetch_and_add_arm)
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.type _(fetch_and_add_arm), %function
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_(fetch_and_add_arm):
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mcr p15, #0, r0, c7, c10, #5
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.L0:
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ldrex r3, [r0]
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add r3, r3, r1
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strex r2, r3, [r0]
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cmp r2, #0
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bne .L0
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mcr p15, #0, r0, c7, c10, #5
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bx lr
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.size _(fetch_and_add_arm), .-_(fetch_and_add_arm)
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.global _(__atomic_test_and_set)
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.type _(__atomic_test_and_set), %function
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_(__atomic_test_and_set):
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#ifdef __TINYC__
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.int 0xe92d4030
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.int 0xee070fba
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.int 0xe5d03000
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.int 0xe24dd014
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.int 0xe1a05000
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.int 0xe2533000
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.int 0xe1a04001
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.int 0x13a03001
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.int 0xee070fba
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.int 0xe5cd300f
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.int 0xe3a03001
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.int 0xe1a02003
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.int 0xe28d100f
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.int 0xe1a00005
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.int 0xe58d4004
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.int 0xe58d4000
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.int 0xeb000009
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.int 0xe3500000
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.int 0x0afffff6
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.int 0xe5dd000f
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.int 0xe28dd014
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.int 0xe8bd8030
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#else
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push {r4, r5, lr}
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mcr p15, 0, r0, c7, c10, 5
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ldrb r3, [r0]
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sub sp, sp, #20
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mov r5, r0
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subs r3, r3, #0
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mov r4, r1
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movne r3, #1
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mcr p15, 0, r0, c7, c10, 5
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strb r3, [sp, #15]
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.L20:
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mov r3, #1
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mov r2, r3
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add r1, sp, #15
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mov r0, r5
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str r4, [sp, #4]
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str r4, [sp]
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bl __atomic_compare_exchange_1
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cmp r0, #0
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beq .L20
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ldrb r0, [sp, #15]
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add sp, sp, #20
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pop {r4, r5, pc}
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#endif
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.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
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.global _(__atomic_clear)
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.type _(__atomic_clear), %function
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_(__atomic_clear):
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#ifdef __TINYC__
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.int 0xe3a03000
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.int 0xee070fba
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.int 0xe5c03000
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.int 0xee070fba
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.int 0xe12fff1e
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#else
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mov r3, #0
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mcr p15, 0, r0, c7, c10, 5
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strb r3, [r0]
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mcr p15, 0, r0, c7, c10, 5
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bx lr
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#endif
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.size _(__atomic_clear), .-_(__atomic_clear)
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.global _(__atomic_compare_exchange_1)
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.type _(__atomic_compare_exchange_1), %function
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_(__atomic_compare_exchange_1):
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@ -141,6 +268,67 @@ _(__atomic_compare_exchange_4):
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.text
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.align 2
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.global _(fetch_and_add_arm64)
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.type _(fetch_and_add_arm64), %function
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_(fetch_and_add_arm64):
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#ifdef __TINYC__
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.int 0x885f7c02
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.int 0x0b010042
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.int 0x8803fc02
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.int 0x35ffffa3
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.int 0xd5033bbf
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.int 0xd65f03c0
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#else
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ldxr w2, [x0]
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add w2, w2, w1
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stlxr w3, w2, [x0]
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cbnz w3, _(fetch_and_add_arm64)
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dmb ish
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ret
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#endif
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.size _(fetch_and_add_arm64), .-_(fetch_and_add_arm64)
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.global _(__atomic_test_and_set)
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.type _(__atomic_test_and_set), %function
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_(__atomic_test_and_set):
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#ifdef __TINYC__
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.int 0xa9bf7bfd
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.int 0xaa0003e1
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.int 0x52800020
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.int 0x910003fd
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.int 0x2a0003f0
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.int 0x085ffc20
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.int 0x0811fc30
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.int 0x35ffffd1
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.int 0xa8c17bfd
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.int 0xd65f03c0
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#else
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stp x29, x30, [sp, -16]!
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mov x1, x0
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mov w0, 1
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mov x29, sp
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mov w16, w0
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.L20:
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ldaxrb w0, [x1]
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stlxrb w17, w16, [x1]
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cbnz w17, .L20
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ldp x29, x30, [sp], 16
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ret
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#endif
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.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
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.global _(__atomic_clear)
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.type _(__atomic_clear), %function
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_(__atomic_clear):
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#ifdef __TINYC__
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.int 0x089ffc1f
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.int 0xd65f03c0
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#else
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stlrb wzr, [x0]
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ret
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#endif
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.size _(__atomic_clear), .-_(__atomic_clear)
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.global _(__atomic_compare_exchange_1)
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.type _(__atomic_compare_exchange_1), %function
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_(__atomic_compare_exchange_1):
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@ -367,6 +555,63 @@ _(__atomic_compare_exchange_8):
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.text
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.align 2
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.global _(fetch_and_add_riscv64)
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.type _(fetch_and_add_riscv64), %function
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_(fetch_and_add_riscv64):
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#ifdef __TINYC__
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.int 0x0f50000f
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.int 0x004b5202f
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.short 0x8082
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#else
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fence iorw,ow
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amoadd.w.aq zero,a1,0(a0)
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ret
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#endif
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.size _(fetch_and_add_riscv64), .-_(fetch_and_add_riscv64)
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.global _(__atomic_test_and_set)
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.type _(__atomic_test_and_set), %function
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_(__atomic_test_and_set):
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#ifdef __TINYC__
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.int 0x00357793
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.int 0x0037979b
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.short 0x4685
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.short 0x9971
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.int 0x00f696bb
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.int 0x0f50000f
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.int 0x44d5272f
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.int 0x00f7553b
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.int 0x0ff57513
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.short 0x8082
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#else
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andi a5,a0,3
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slliw a5,a5,3
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li a3,1
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andi a0,a0,-4
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sllw a3,a3,a5
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fence iorw,ow; amoor.w.aq a4,a3,0(a0)
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srlw a0,a4,a5
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andi a0,a0,0xff
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ret
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#endif
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.size _(__atomic_test_and_set), .-_(__atomic_test_and_set)
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.global _(__atomic_clear)
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.type _(__atomic_clear), %function
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_(__atomic_clear):
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#ifdef __TINYC__
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.int 0x0ff0000f
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.int 0x00050023
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.int 0x0ff0000f
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.short 0x8082
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#else
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fence iorw,iorw
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sb zero,0(a0)
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fence iorw,iorw
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ret
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#endif
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.size _(__atomic_clear), .-_(__atomic_clear)
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.global _(__atomic_compare_exchange_1)
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.type _(__atomic_compare_exchange_1), %function
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_(__atomic_compare_exchange_1):
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@ -1,76 +0,0 @@
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/* ---------------------------------------------- */
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#ifdef __leading_underscore
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# define _(s) _##s
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#else
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# define _(s) s
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#endif
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.globl _(__bound_alloca)
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_(__bound_alloca):
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#if defined __arm__
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.text
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.align 2
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.global _(fetch_and_add_arm)
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.type _(fetch_and_add_arm), %function
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_(fetch_and_add_arm):
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mcr p15, #0, r0, c7, c10, #5
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.L0:
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ldrex r3, [r0]
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add r3, r3, r1
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strex r2, r3, [r0]
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cmp r2, #0
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bne .L0
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mcr p15, #0, r0, c7, c10, #5
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bx lr
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.size _(fetch_and_add_arm), .-_(fetch_and_add_arm)
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/* ---------------------------------------------- */
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#elif defined __aarch64__
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.text
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.align 2
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.global _(fetch_and_add_arm64)
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.type _(fetch_and_add_arm64), %function
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_(fetch_and_add_arm64):
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#ifdef __TINYC__
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.int 0x885f7c02
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.int 0x0b010042
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.int 0x8803fc02
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.int 0x35ffffa3
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.int 0xd5033bbf
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.int 0xd65f03c0
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#else
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ldxr w2, [x0]
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add w2, w2, w1
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stlxr w3, w2, [x0]
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cbnz w3, _(fetch_and_add_arm64)
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dmb ish
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ret
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#endif
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.size _(fetch_and_add_arm64), .-_(fetch_and_add_arm64)
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/* ---------------------------------------------- */
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#elif defined __riscv
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.text
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.align 2
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.global _(fetch_and_add_riscv64)
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.type _(fetch_and_add_riscv64), %function
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_(fetch_and_add_riscv64):
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#ifdef __TINYC__
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.int 0x0f50000f
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.int 0x004b5202f
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.short 0x8082
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#else
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fence iorw,ow
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amoadd.w.aq zero,a1,0(a0)
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ret
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#endif
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.size _(fetch_and_add_riscv64), .-_(fetch_and_add_riscv64)
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/* ---------------------------------------------- */
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#endif
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@ -23,7 +23,7 @@ typedef __SIZE_TYPE__ size_t;
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{ \
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TYPE rv; \
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TYPE cmp = *(TYPE *)ref; \
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asm volatile( \
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__asm__ volatile( \
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"lock cmpxchg" SUFFIX " %2,%1\n" \
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: "=a" (rv), "+m" (*(TYPE *)atom) \
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: "q" (xchg), "0" (cmp) \
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@ -115,16 +115,6 @@ ATOMIC_GEN(uint32_t, 4, "l")
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ATOMIC_GEN(uint64_t, 8, "q")
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#endif
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bool __atomic_test_and_set (volatile void *ptr, int memorder)
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{
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return __atomic_exchange_1(ptr, 1, memorder);
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}
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void __atomic_clear (volatile void *ptr, int memorder)
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{
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__atomic_store_1(ptr, 0, memorder);
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}
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void __atomic_signal_fence (int memorder)
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{
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}
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@ -132,15 +122,15 @@ void __atomic_signal_fence (int memorder)
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void __atomic_thread_fence (int memorder)
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{
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#if defined __i386__
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asm volatile("lock orl $0, (%esp)");
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__asm__ volatile("lock orl $0, (%esp)");
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#elif defined __x86_64__
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asm volatile("lock orq $0, (%rsp)");
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__asm__ volatile("lock orq $0, (%rsp)");
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#elif defined __arm__
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asm volatile(".int 0xee070fba"); // mcr p15, 0, r0, c7, c10, 5
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__asm__ volatile(".int 0xee070fba"); // mcr p15, 0, r0, c7, c10, 5
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#elif defined __aarch64__
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asm volatile(".int 0xd5033bbf"); // dmb ish
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__asm__ volatile(".int 0xd5033bbf"); // dmb ish
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#elif defined __riscv
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asm volatile(".int 0x0ff0000f"); // fence iorw,iorw
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__asm__ volatile(".int 0x0ff0000f"); // fence iorw,iorw
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#endif
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}
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@ -14,11 +14,9 @@
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abort(); \
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} while (0)
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#ifndef __APPLE__
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#if defined __x86_64__ || defined __aarch64__ || defined __riscv
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#define HAS_64BITS
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#endif
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#endif
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typedef struct {
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atomic_flag flag;
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||||
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