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riscv: asm: Add load-reserved and store-conditional
Add Atomic instructions `ld` and `sc` in their 32 bit and 64 bit versions.
This commit is contained in:
Ekaitz Zarraga
parent
0703df1a6a
commit
c994068175
119
riscv64-asm.c
119
riscv64-asm.c
@ -51,6 +51,7 @@ typedef struct Operand {
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static void asm_binary_opcode(TCCState* s1, int token);
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ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str);
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ST_FUNC void asm_compute_constraints(ASMOperand *operands, int nb_operands, int nb_outputs, const uint8_t *clobber_regs, int *pout_reg);
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static void asm_emit_a(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *rd1, int aq, int rl);
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static void asm_emit_b(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm);
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static void asm_emit_i(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2);
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static void asm_emit_j(int token, uint32_t opcode, const Operand *rd, const Operand *rs2);
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@ -1044,6 +1045,102 @@ static void asm_ternary_opcode(TCCState *s1, int token)
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}
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}
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static void asm_atomic_opcode(TCCState *s1, int token)
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{
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static const Operand zero = {.type = OP_REG};
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Operand ops[3];
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parse_operand(s1, &ops[0]);
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if ( tok == ',') next(); else expect("','");
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if ( token <= TOK_ASM_lr_d_aqrl && token >= TOK_ASM_lr_w ) {
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ops[1] = zero;
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} else {
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parse_operand(s1, &ops[1]);
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if ( tok == ',') next(); else expect("','");
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}
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if ( tok == '(') next(); else expect("'('");
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parse_operand(s1, &ops[2]);
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if ( tok == ')') next(); else expect("')'");
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switch(token){
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case TOK_ASM_lr_w:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 0);
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break;
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case TOK_ASM_lr_w_aq:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 0);
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break;
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case TOK_ASM_lr_w_rl:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 1);
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break;
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case TOK_ASM_lr_w_aqrl:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 1);
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break;
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case TOK_ASM_lr_d:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 0);
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break;
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case TOK_ASM_lr_d_aq:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 0);
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break;
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case TOK_ASM_lr_d_rl:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 1);
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break;
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case TOK_ASM_lr_d_aqrl:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 1);
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break;
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case TOK_ASM_sc_w:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 0);
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break;
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case TOK_ASM_sc_w_aq:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 0);
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break;
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case TOK_ASM_sc_w_rl:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 1);
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break;
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case TOK_ASM_sc_w_aqrl:
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asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 1);
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break;
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case TOK_ASM_sc_d:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 0);
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break;
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case TOK_ASM_sc_d_aq:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 0);
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break;
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case TOK_ASM_sc_d_rl:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 1);
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break;
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case TOK_ASM_sc_d_aqrl:
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asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 1);
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break;
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}
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}
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/* caller: Add funct3 and func5 to opcode */
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static void asm_emit_a(int token, uint32_t opcode, const Operand *rd1, const Operand *rs2, const Operand *rs1, int aq, int rl)
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{
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if (rd1->type != OP_REG)
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tcc_error("'%s': Expected first destination operand that is a register", get_tok_str(token, NULL));
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if (rs2->type != OP_REG)
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tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token, NULL));
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if (rs1->type != OP_REG)
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tcc_error("'%s': Expected third source operand that is a register", get_tok_str(token, NULL));
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/* A-type instruction:
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31...27 funct5
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26 aq
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25 rl
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24...20 rs2
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19...15 rs1
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14...11 funct3
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11...7 rd
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6...0 opcode
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opcode always fixed pos. */
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gen_le32(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | ENCODE_RD(rd1->reg) | aq << 26 | rl << 25);
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}
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/* caller: Add funct3 to opcode */
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static void asm_emit_s(int token, uint32_t opcode, const Operand* rs1, const Operand* rs2, const Operand* imm)
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{
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@ -1109,7 +1206,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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switch (token) {
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case TOK_ASM_ebreak:
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case TOK_ASM_ecall:
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case TOK_ASM_fence:
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case TOK_ASM_fence: // XXX: it's missing iorw for pred and succ
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case TOK_ASM_fence_i:
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case TOK_ASM_hrts:
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case TOK_ASM_mrth:
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@ -1306,6 +1403,26 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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asm_ternary_opcode(s1, token);
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return;
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/* Atomic operations */
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case TOK_ASM_lr_w:
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case TOK_ASM_lr_w_aq:
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case TOK_ASM_lr_w_rl:
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case TOK_ASM_lr_w_aqrl:
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case TOK_ASM_lr_d:
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case TOK_ASM_lr_d_aq:
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case TOK_ASM_lr_d_rl:
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case TOK_ASM_lr_d_aqrl:
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case TOK_ASM_sc_w:
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case TOK_ASM_sc_w_aq:
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case TOK_ASM_sc_w_rl:
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case TOK_ASM_sc_w_aqrl:
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case TOK_ASM_sc_d:
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case TOK_ASM_sc_d_aq:
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case TOK_ASM_sc_d_rl:
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case TOK_ASM_sc_d_aqrl:
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asm_atomic_opcode(s1, token);
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break;
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default:
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expect("known instruction");
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}
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@ -8,6 +8,9 @@
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#define DEF_ASM_WITH_SUFFIX(x, y) \
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DEF(TOK_ASM_ ## x ## _ ## y, #x "." #y)
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#define DEF_ASM_WITH_SUFFIXES(x, y, z) \
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DEF(TOK_ASM_ ## x ## _ ## y ## _ ## z, #x "." #y "." #z)
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/* register */
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/* integer */
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DEF_ASM(x0)
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@ -422,4 +425,27 @@
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DEF_ASM(push)
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DEF_ASM(pop)
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/* “A” Standard Extension for Atomic Instructions, Version 2.1 */
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/* XXX: Atomic memory operations */
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DEF_ASM_WITH_SUFFIX(lr, w)
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DEF_ASM_WITH_SUFFIXES(lr, w, aq)
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DEF_ASM_WITH_SUFFIXES(lr, w, rl)
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DEF_ASM_WITH_SUFFIXES(lr, w, aqrl)
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DEF_ASM_WITH_SUFFIX(lr, d)
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DEF_ASM_WITH_SUFFIXES(lr, d, aq)
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DEF_ASM_WITH_SUFFIXES(lr, d, rl)
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DEF_ASM_WITH_SUFFIXES(lr, d, aqrl)
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DEF_ASM_WITH_SUFFIX(sc, w)
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DEF_ASM_WITH_SUFFIXES(sc, w, aq)
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DEF_ASM_WITH_SUFFIXES(sc, w, rl)
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DEF_ASM_WITH_SUFFIXES(sc, w, aqrl)
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DEF_ASM_WITH_SUFFIX(sc, d)
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DEF_ASM_WITH_SUFFIXES(sc, d, aq)
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DEF_ASM_WITH_SUFFIXES(sc, d, rl)
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DEF_ASM_WITH_SUFFIXES(sc, d, aqrl)
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#undef DEF_ASM_WITH_SUFFIX
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