From c0368604e196d53b281cd2aceb140b5facd36ed7 Mon Sep 17 00:00:00 2001
From: Michael Matz <matz@suse.de>
Date: Sat, 6 Aug 2016 23:19:04 +0200
Subject: [PATCH] x86-64-asm: Fix ltr/str and push/pop operands

str accepts rm16/r32/r64, and push/pop defaults to 64 when given
memory operands (to 32 on i386).
---
 i386-asm.c      | 3 +++
 tests/asmtest.S | 5 +++++
 x86_64-asm.h    | 6 ++++--
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/i386-asm.c b/i386-asm.c
index 5d7ee684..dd8bb989 100644
--- a/i386-asm.c
+++ b/i386-asm.c
@@ -869,6 +869,9 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
             if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
                 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
                 s = 2;
+	    else if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
+		     (ops[0].type & OP_EA))
+	        s = NBWLX - 2;
             else
                 tcc_error("cannot infer opcode suffix");
         }
diff --git a/tests/asmtest.S b/tests/asmtest.S
index a565ec0e..10ec2ee0 100644
--- a/tests/asmtest.S
+++ b/tests/asmtest.S
@@ -125,6 +125,8 @@ notl %r15d
   push %gs
   push $1
   push $100
+  push 0x42(%eax)
+  pop 0x43(%esi)
                                                 
 #ifdef __i386__
   popl %eax
@@ -740,8 +742,11 @@ int $0x10
     lmsw 0x1000
     lsl 0x1000, %ecx
     ltr 0x1000
+    ltr %si
     smsw 0x1000
     str 0x1000
+    str %ecx
+    str %dx
     
     verr 0x1000
     verw 0x1000
diff --git a/x86_64-asm.h b/x86_64-asm.h
index c9d22934..4db32687 100644
--- a/x86_64-asm.h
+++ b/x86_64-asm.h
@@ -367,14 +367,16 @@ ALT(DEF_ASM_OP2(larw, 0x0f02, 0, OPC_MODRM | OPC_WLX, OPT_REG | OPT_EA, OPT_REG)
     DEF_ASM_OP1(lldt, 0x0f00, 2, OPC_MODRM, OPT_EA | OPT_REG)
     DEF_ASM_OP1(lmsw, 0x0f01, 6, OPC_MODRM, OPT_EA | OPT_REG)
 ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM | OPC_WLX, OPT_EA | OPT_REG, OPT_REG))
-    DEF_ASM_OP1(ltr, 0x0f00, 3, OPC_MODRM, OPT_EA | OPT_REG)
+    DEF_ASM_OP1(ltr, 0x0f00, 3, OPC_MODRM, OPT_EA | OPT_REG16)
     DEF_ASM_OP1(sgdt, 0x0f01, 0, OPC_MODRM, OPT_EA)
     DEF_ASM_OP1(sgdtq, 0x0f01, 0, OPC_MODRM, OPT_EA)
     DEF_ASM_OP1(sidt, 0x0f01, 1, OPC_MODRM, OPT_EA)
     DEF_ASM_OP1(sidtq, 0x0f01, 1, OPC_MODRM, OPT_EA)
     DEF_ASM_OP1(sldt, 0x0f00, 0, OPC_MODRM, OPT_REG | OPT_EA)
     DEF_ASM_OP1(smsw, 0x0f01, 4, OPC_MODRM, OPT_REG | OPT_EA)
-    DEF_ASM_OP1(str, 0x0f00, 1, OPC_MODRM, OPT_REG16| OPT_EA)
+    DEF_ASM_OP1(str, 0x0f00, 1, OPC_MODRM, OPT_REG32 | OPT_EA)
+ALT(DEF_ASM_OP1(str, 0x660f00, 1, OPC_MODRM, OPT_REG16))
+ALT(DEF_ASM_OP1(str, 0x480f00, 1, OPC_MODRM, OPT_REG64))
     DEF_ASM_OP1(verr, 0x0f00, 4, OPC_MODRM, OPT_REG | OPT_EA)
     DEF_ASM_OP1(verw, 0x0f00, 5, OPC_MODRM, OPT_REG | OPT_EA)
     DEF_ASM_OP0L(swapgs, 0x0f01, 7, OPC_MODRM)