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x86-64-asm: Clean up 64bit immediate support
Fix it to actually be able to parse 64bit immediates (enlarge operand value type). Then, generally there's no need for accepting IM64 anywhere, except in the 0xba+r mov opcodes, so OP_IM is unnecessary, as is OPT_IMNO64. Improve the generated code a bit by preferring the 0xc7 opcode for im32->reg64, instead of the im64->reg64 form (which we therefore hardcode).
This commit is contained in:
Michael Matz
parent
f3cee9ceff
commit
b9f01dffc6
34
i386-asm.c
34
i386-asm.c
@ -83,13 +83,10 @@ enum {
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OPT_INDIR, /* *(expr) */
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/* composite types */
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OPT_COMPOSITE_FIRST,
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OPT_IM, /* IM8 | IM16 | IM32 | IM64 */
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OPT_IM, /* IM8 | IM16 | IM32 */
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OPT_REG, /* REG8 | REG16 | REG32 | REG64 */
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OPT_REGW, /* REG16 | REG32 | REG64 */
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OPT_IMW, /* IM16 | IM32 | IM64 */
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#ifdef TCC_TARGET_X86_64
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OPT_IMNO64, /* IM16 | IM32 */
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#endif
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OPT_IMW, /* IM16 | IM32 */
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/* can be ored with any OPT_xxx */
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OPT_EA = 0x80
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};
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@ -128,12 +125,10 @@ enum {
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#define OP_REG (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
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#ifdef TCC_TARGET_X86_64
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# define OP_IM OP_IM64
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# define TREG_XAX TREG_RAX
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# define TREG_XCX TREG_RCX
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# define TREG_XDX TREG_RDX
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#else
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# define OP_IM OP_IM32
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# define TREG_XAX TREG_EAX
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# define TREG_XCX TREG_ECX
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# define TREG_XDX TREG_EDX
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@ -347,7 +342,7 @@ static void parse_operand(TCCState *s1, Operand *op)
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/* constant value */
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next();
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asm_expr(s1, &e);
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op->type = OP_IM;
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op->type = OP_IM32;
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op->e.v = e.v;
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op->e.sym = e.sym;
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if (!op->e.sym) {
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@ -358,8 +353,8 @@ static void parse_operand(TCCState *s1, Operand *op)
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if (op->e.v == (uint16_t)op->e.v)
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op->type |= OP_IM16;
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#ifdef TCC_TARGET_X86_64
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if (op->e.v == (uint32_t)op->e.v)
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op->type |= OP_IM32;
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if (op->e.v != (uint32_t)op->e.v)
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op->type = OP_IM64;
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#endif
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}
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} else {
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@ -587,6 +582,14 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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}
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if (pa->nb_ops != nb_ops)
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continue;
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#ifdef TCC_TARGET_X86_64
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/* Special case for moves. Selecting the IM64->REG64 form
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should only be done if we really have an >32bit imm64, and that
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is hardcoded. Ignore it here. */
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if (pa->opcode == 0xb0 && ops[0].type != OP_IM64
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&& ops[1].type == OP_REG64)
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continue;
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#endif
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/* now decode and check each operand */
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alltypes = 0;
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for(i = 0; i < nb_ops; i++) {
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@ -595,7 +598,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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op2 = op1 & 0x1f;
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switch(op2) {
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case OPT_IM:
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v = OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64;
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v = OP_IM8 | OP_IM16 | OP_IM32;
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break;
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case OPT_REG:
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v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
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@ -604,13 +607,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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v = OP_REG16 | OP_REG32 | OP_REG64;
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break;
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case OPT_IMW:
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v = OP_IM16 | OP_IM32 | OP_IM64;
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break;
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#ifdef TCC_TARGET_X86_64
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case OPT_IMNO64:
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v = OP_IM16 | OP_IM32;
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break;
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#endif
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default:
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v = 1 << op2;
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break;
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@ -647,7 +645,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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#ifdef TCC_TARGET_X86_64
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/* XXX the autosize should rather be zero, to not have to adjust this
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all the time. */
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if ((pa->instr_type & OPC_WLQ) != OPC_WLQ)
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if ((pa->instr_type & OPC_BWLQ) == OPC_B)
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autosize = NBWLX-2;
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#endif
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if (s == autosize) {
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@ -657,7 +655,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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}
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if (s == autosize) {
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if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
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(ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
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(ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
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s = 2;
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else
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tcc_error("cannot infer opcode suffix");
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2
tcc.h
2
tcc.h
@ -610,7 +610,7 @@ typedef struct CachedInclude {
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#ifdef CONFIG_TCC_ASM
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typedef struct ExprValue {
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uint32_t v;
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uint64_t v;
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Sym *sym;
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} ExprValue;
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3
tccasm.c
3
tccasm.c
@ -41,7 +41,8 @@ static Sym sym_dot;
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static void asm_expr_unary(TCCState *s1, ExprValue *pe)
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{
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Sym *sym;
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int op, n, label;
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int op, label;
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long n;
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const char *p;
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switch(tok) {
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@ -46,6 +46,16 @@ movl %eax, 0x100(%ebx,%edx,2)
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movl 0x100(%ebx,%edx,2), %edx
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movw %ax, 0x100(%ebx,%edx,2)
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movw $0x1122,%si
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movl $0x112233,%edx
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#ifdef __x86_64__
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mov $0x11223344,%rbx
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movq $0x11223344,%rbx
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mov $0x1122334455,%rbx
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movq $0x1122334455,%rbx
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movl $0x11334455,(%rbx)
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#endif
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mov %eax, 0x12(,%edx,2)
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#ifdef __i386__
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14
x86_64-asm.h
14
x86_64-asm.h
@ -97,7 +97,13 @@ ALT(DEF_ASM_OP2(movb, 0xa0, 0, OPC_BWLQ, OPT_ADDR, OPT_EAX))
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ALT(DEF_ASM_OP2(movb, 0xa2, 0, OPC_BWLQ, OPT_EAX, OPT_ADDR)) */
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ALT(DEF_ASM_OP2(movb, 0x88, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_EA | OPT_REG))
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ALT(DEF_ASM_OP2(movb, 0x8a, 0, OPC_MODRM | OPC_BWLQ, OPT_EA | OPT_REG, OPT_REG))
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/* The moves are special: the 0xb8 form supports IM64 (the only insn that
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does) with REG64. It doesn't support IM32 with REG64, it would use
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the full movabs form (64bit immediate). For IM32->REG64 we prefer
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the 0xc7 opcode. So disallow all 64bit forms and code the rest by hand. */
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ALT(DEF_ASM_OP2(movb, 0xb0, 0, OPC_REG | OPC_BWLQ, OPT_IM, OPT_REG))
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ALT(DEF_ASM_OP2(mov, 0x48b8, 0, OPC_REG, OPT_IM64, OPT_REG64))
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ALT(DEF_ASM_OP2(movq, 0x48b8, 0, OPC_REG, OPT_IM64, OPT_REG64))
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ALT(DEF_ASM_OP2(movb, 0xc6, 0, OPC_MODRM | OPC_BWLQ, OPT_IM, OPT_REG | OPT_EA))
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ALT(DEF_ASM_OP2(movw, 0x8c, 0, OPC_MODRM | OPC_WLQ, OPT_SEG, OPT_EA | OPT_REG))
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@ -156,14 +162,14 @@ ALT(DEF_ASM_OP2(lgs, 0x0fb5, 0, OPC_MODRM, OPT_EA, OPT_REG32))
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/* arith */
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ALT(DEF_ASM_OP2(addb, 0x00, 0, OPC_ARITH | OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_EA | OPT_REG)) /* XXX: use D bit ? */
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ALT(DEF_ASM_OP2(addb, 0x02, 0, OPC_ARITH | OPC_MODRM | OPC_BWLQ, OPT_EA | OPT_REG, OPT_REG))
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ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWLQ, OPT_IMNO64, OPT_EAX))
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ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLQ, OPT_IMNO64, OPT_EA | OPT_REG))
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ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWLQ, OPT_IM, OPT_EAX))
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ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLQ, OPT_IM, OPT_EA | OPT_REG))
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ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WLQ, OPT_IM8S, OPT_EA | OPT_REG))
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ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_EA | OPT_REG))
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ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLQ, OPT_EA | OPT_REG, OPT_REG))
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ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWLQ, OPT_IMNO64, OPT_EAX))
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ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM | OPC_BWLQ, OPT_IMNO64, OPT_EA | OPT_REG))
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ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWLQ, OPT_IM, OPT_EAX))
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ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM | OPC_BWLQ, OPT_IM, OPT_EA | OPT_REG))
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ALT(DEF_ASM_OP1(incb, 0xfe, 0, OPC_MODRM | OPC_BWLQ, OPT_REG | OPT_EA))
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ALT(DEF_ASM_OP1(decb, 0xfe, 1, OPC_MODRM | OPC_BWLQ, OPT_REG | OPT_EA))
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