mirror of
https://github.com/mirror/tinycc.git
synced 2025-01-13 05:10:07 +08:00
Use arm assembler in lib dir
This commit is contained in:
parent
bc6c0c34c1
commit
b40a88ea46
@ -3,15 +3,8 @@
|
||||
.global alloca
|
||||
.type alloca, %function
|
||||
alloca:
|
||||
#ifdef __TINYC__
|
||||
.int 0xe060d00d
|
||||
.int 0xe3cdd007
|
||||
.int 0xe1a0000d
|
||||
.int 0xe1a0f00e
|
||||
#else
|
||||
rsb sp, r0, sp
|
||||
bic sp, sp, #7
|
||||
mov r0, sp
|
||||
mov pc, lr
|
||||
#endif
|
||||
.size alloca, .-alloca
|
||||
|
@ -13,13 +13,13 @@ unsigned _tccsyscall(unsigned syscall_nr, ...);
|
||||
__asm__(
|
||||
".global _tccsyscall\n"
|
||||
"_tccsyscall:\n"
|
||||
".int 0xe92d4080\n" // push {r7, lr}
|
||||
".int 0xe1a07000\n" // mov r7, r0
|
||||
".int 0xe1a00001\n" // mov r0, r1
|
||||
".int 0xe1a01002\n" // mov r1, r2
|
||||
".int 0xe1a02003\n" // mov r2, r3
|
||||
".int 0xef000000\n" // svc 0x00000000
|
||||
".int 0xe8bd8080\n" // pop {r7, pc}
|
||||
"push {r7, lr}\n\t"
|
||||
"mov r7, r0\n\t"
|
||||
"mov r0, r1\n\t"
|
||||
"mov r1, r2\n\t"
|
||||
"mov r2, r3\n\t"
|
||||
"svc #0\n\t"
|
||||
"pop {r7, pc}"
|
||||
);
|
||||
|
||||
/* from unistd.h: */
|
||||
@ -47,14 +47,5 @@ void __clear_cache(void *beginning, void *end)
|
||||
{
|
||||
/* __ARM_NR_cacheflush is kernel private and should not be used in user space.
|
||||
* However, there is no ARM asm parser in tcc so we use it for now */
|
||||
#if 1
|
||||
syscall(__ARM_NR_cacheflush, beginning, end, 0);
|
||||
#else
|
||||
__asm__ ("push {r7}\n\t"
|
||||
"mov r7, #0xf0002\n\t"
|
||||
"mov r2, #0\n\t"
|
||||
"swi 0\n\t"
|
||||
"pop {r7}\n\t"
|
||||
"ret");
|
||||
#endif
|
||||
}
|
||||
|
@ -3,26 +3,13 @@
|
||||
.global fetch_and_add_arm
|
||||
.type fetch_and_add_arm, %function
|
||||
fetch_and_add_arm:
|
||||
#ifdef __TINYC__
|
||||
.int 0xee070fba
|
||||
.int 0xe1903f9f
|
||||
.int 0xe0833001
|
||||
.int 0xe1802f93
|
||||
.int 0xe3520000
|
||||
.int 0x1afffffa
|
||||
.int 0xee070fba
|
||||
.int 0xe12fff1e
|
||||
#else
|
||||
.arch armv6
|
||||
|
||||
mcr p15, 0, r0, c7, c10, 5
|
||||
mcr p15, #0, r0, c7, c10, #5
|
||||
.L0:
|
||||
ldrex r3, [r0]
|
||||
add r3, r3, r1
|
||||
strex r2, r3, [r0]
|
||||
cmp r2, #0
|
||||
bne .L0
|
||||
mcr p15, 0, r0, c7, c10, 5
|
||||
mcr p15, #0, r0, c7, c10, #5
|
||||
bx lr
|
||||
#endif
|
||||
.size fetch_and_add_arm, .-fetch_and_add_arm
|
||||
|
Loading…
Reference in New Issue
Block a user