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Architecture-specific section alignment
Tests found excessive cache thrashing on x86-64 architectures. The problem was traced to the alignment of sections. This patch sets up an architecture-specific alignment of 512 bytes for x86-64 and 16 bytes for all others. It uses preprocessor directives that, hopefully, make it easy to tweak for other architectures.
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8
tccrun.c
8
tccrun.c
@ -174,6 +174,12 @@ LIBTCCAPI int tcc_run(TCCState *s1, int argc, char **argv)
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return (*prog_main)(argc, argv);
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}
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#ifdef TCC_TARGET_X86_64
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#define SECTION_ALIGNMENT 511
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#else
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#define SECTION_ALIGNMENT 15
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#endif
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/* relocate code. Return -1 on error, required size if ptr is NULL,
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otherwise copy code into buffer passed by the caller */
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static int tcc_relocate_ex(TCCState *s1, void *ptr)
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@ -205,7 +211,7 @@ static int tcc_relocate_ex(TCCState *s1, void *ptr)
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s = s1->sections[i];
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if (0 == (s->sh_flags & SHF_ALLOC))
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continue;
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offset = (offset + 15) & ~15;
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offset = (offset + SECTION_ALIGNMENT) & ~SECTION_ALIGNMENT;
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s->sh_addr = mem ? mem + offset : 0;
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offset += s->data_offset;
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}
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