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x86-64-asm: Fix mov im64,rax encoding
the avoidance of mov im32->reg64 wasn't working when reg64 was rax. While fixing this also fix instructions which had the REX prefix hardcoded in opcode and so didn't support extended registers which would have added another REX prefix.
This commit is contained in:
Michael Matz
parent
e209b7dac4
commit
3e4c296eba
11
i386-asm.c
11
i386-asm.c
@ -42,6 +42,7 @@
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#define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
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#define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
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#define OPC_48 0x200 /* Always has REX prefix */
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#ifdef TCC_TARGET_X86_64
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# define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
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# define OPC_BWLQ (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
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@ -785,7 +786,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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should only be done if we really have an >32bit imm64, and that
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is hardcoded. Ignore it here. */
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if (pa->opcode == 0xb0 && ops[0].type != OP_IM64
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&& ops[1].type == OP_REG64
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&& (ops[1].type & OP_REG) == OP_REG64
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&& !(pa->instr_type & OPC_0F))
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continue;
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#endif
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@ -901,14 +902,16 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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g(0x66);
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#ifdef TCC_TARGET_X86_64
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rex64 = 0;
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if (s == 3 || (alltypes & OP_REG64)) {
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if (pa->instr_type & OPC_48)
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rex64 = 1;
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else if (s == 3 || (alltypes & OP_REG64)) {
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/* generate REX prefix */
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int default64 = 0;
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for(i = 0; i < nb_ops; i++) {
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if (op_type[i] == OP_REG64) {
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if (op_type[i] == OP_REG64 && pa->opcode != 0xb8) {
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/* If only 64bit regs are accepted in one operand
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this is a default64 instruction without need for
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REX prefixes. */
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REX prefixes, except for movabs(0xb8). */
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default64 = 1;
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break;
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}
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@ -114,12 +114,21 @@ notl %r15d
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movzb 0x1000, %eax
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movzb 0x1000, %ax
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mov $0x12345678,%eax
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#ifdef __x86_64__
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movzb 0x1000, %rax
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movzbq 0x1000, %rbx
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movsbq 0x1000, %rdx
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movzwq 0x1000, %rdi
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movswq 0x1000, %rdx
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movslq %eax, %rcx
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mov $0x12345678,%rax
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mov $0x12345678,%rdx
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mov $0x12345678,%r10
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mov $0x123456789abcdef0,%rax
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mov $0x123456789abcdef0,%rcx
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mov $0x123456789abcdef0,%r11
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#endif
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#ifdef __i386__
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@ -546,6 +555,7 @@ invlpg 0x1000
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cmpxchg8b 0x1002
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#ifdef __x86_64__
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cmpxchg16b (%rax)
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cmpxchg16b (%r10,%r11)
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#endif
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fcmovb %st(5), %st
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@ -569,6 +579,7 @@ fucomip %st(5), %st
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cmovne %ax, %si
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#ifdef __x86_64__
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bswapq %rsi
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bswapq %r10
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cmovz %rdi,%rbx
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#endif
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@ -675,7 +686,9 @@ int $0x10
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prefetchw (%rdi)
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clflush 0x1000(%rax,%rcx)
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fxsaveq (%rdx)
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fxsaveq (%r11)
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fxrstorq (%rcx)
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fxrstorq (%r10)
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#endif
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@ -751,6 +764,9 @@ int $0x10
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sidtq 0x1000
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swapgs
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str %rdx
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str %r9
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#endif
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lmsw 0x1000
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@ -879,6 +895,7 @@ overrideme:
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#ifdef __x86_64__
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movq %rcx, %mm1
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movq %rdx, %xmm2
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movq %r13, %xmm3
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/* movq mem64->xmm is encoded as f30f7e by GAS, but as
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660f6e by tcc (which really is a movd and would need
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a REX.W prefix to be movq). */
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18
x86_64-asm.h
18
x86_64-asm.h
@ -106,8 +106,8 @@ ALT(DEF_ASM_OP2(movb, 0x8a, 0, OPC_MODRM | OPC_BWLX, OPT_EA | OPT_REG, OPT_REG))
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the full movabs form (64bit immediate). For IM32->REG64 we prefer
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the 0xc7 opcode. So disallow all 64bit forms and code the rest by hand. */
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ALT(DEF_ASM_OP2(movb, 0xb0, 0, OPC_REG | OPC_BWLX, OPT_IM, OPT_REG))
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ALT(DEF_ASM_OP2(mov, 0x48b8, 0, OPC_REG, OPT_IM64, OPT_REG64))
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ALT(DEF_ASM_OP2(movq, 0x48b8, 0, OPC_REG, OPT_IM64, OPT_REG64))
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ALT(DEF_ASM_OP2(mov, 0xb8, 0, OPC_REG, OPT_IM64, OPT_REG64))
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ALT(DEF_ASM_OP2(movq, 0xb8, 0, OPC_REG, OPT_IM64, OPT_REG64))
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ALT(DEF_ASM_OP2(movb, 0xc6, 0, OPC_MODRM | OPC_BWLX, OPT_IM, OPT_REG | OPT_EA))
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ALT(DEF_ASM_OP2(movw, 0x8c, 0, OPC_MODRM | OPC_WLX, OPT_SEG, OPT_EA | OPT_REG))
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@ -123,7 +123,7 @@ ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movsbq, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REGW))
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ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movswq, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG))
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ALT(DEF_ASM_OP2(movslq, 0x4863, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG))
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ALT(DEF_ASM_OP2(movslq, 0x63, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG))
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ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM | OPC_WLX, OPT_REG8 | OPT_EA, OPT_REGW))
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ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
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ALT(DEF_ASM_OP2(movzwq, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG))
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@ -354,8 +354,8 @@ ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM | OPC_FWAIT, OPT_EA ))
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If the operand would use extended registers we would have to modify
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it instead of generating a second one. Currently that's no
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problem with TCC, we don't use extended registers. */
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DEF_ASM_OP1(fxsaveq, 0x480fae, 0, OPC_MODRM, OPT_EA )
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DEF_ASM_OP1(fxrstorq, 0x480fae, 1, OPC_MODRM, OPT_EA )
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DEF_ASM_OP1(fxsaveq, 0x0fae, 0, OPC_MODRM | OPC_48, OPT_EA )
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DEF_ASM_OP1(fxrstorq, 0x0fae, 1, OPC_MODRM | OPC_48, OPT_EA )
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/* segments */
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DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 | OPT_EA)
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@ -376,7 +376,7 @@ ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM | OPC_WLX, OPT_EA | OPT_REG, OPT_REG)
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DEF_ASM_OP1(smsw, 0x0f01, 4, OPC_MODRM, OPT_REG | OPT_EA)
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DEF_ASM_OP1(str, 0x0f00, 1, OPC_MODRM, OPT_REG32 | OPT_EA)
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ALT(DEF_ASM_OP1(str, 0x660f00, 1, OPC_MODRM, OPT_REG16))
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ALT(DEF_ASM_OP1(str, 0x480f00, 1, OPC_MODRM, OPT_REG64))
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ALT(DEF_ASM_OP1(str, 0x0f00, 1, OPC_MODRM | OPC_48, OPT_REG64))
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DEF_ASM_OP1(verr, 0x0f00, 4, OPC_MODRM, OPT_REG | OPT_EA)
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DEF_ASM_OP1(verw, 0x0f00, 5, OPC_MODRM, OPT_REG | OPT_EA)
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DEF_ASM_OP0L(swapgs, 0x0f01, 7, OPC_MODRM)
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@ -385,7 +385,7 @@ ALT(DEF_ASM_OP1(str, 0x480f00, 1, OPC_MODRM, OPT_REG64))
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/* bswap can't be applied to 16bit regs */
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DEF_ASM_OP1(bswap, 0x0fc8, 0, OPC_REG, OPT_REG32 )
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DEF_ASM_OP1(bswapl, 0x0fc8, 0, OPC_REG, OPT_REG32 )
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DEF_ASM_OP1(bswapq, 0x480fc8, 0, OPC_REG, OPT_REG64 )
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DEF_ASM_OP1(bswapq, 0x0fc8, 0, OPC_REG | OPC_48, OPT_REG64 )
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ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM | OPC_BWLX, OPT_REG, OPT_REG | OPT_EA ))
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ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM | OPC_BWLX, OPT_REG, OPT_REG | OPT_EA ))
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@ -395,7 +395,7 @@ ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM | OPC_BWLX, OPT_REG, OPT_REG | OP
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DEF_ASM_OP1(cmpxchg8b, 0x0fc7, 1, OPC_MODRM, OPT_EA )
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/* AMD 64 */
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DEF_ASM_OP1(cmpxchg16b, 0x480fc7, 1, OPC_MODRM, OPT_EA )
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DEF_ASM_OP1(cmpxchg16b, 0x0fc7, 1, OPC_MODRM | OPC_48, OPT_EA )
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/* pentium pro */
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ALT(DEF_ASM_OP2(cmovo, 0x0f40, 0, OPC_MODRM | OPC_TEST | OPC_WLX, OPT_REGW | OPT_EA, OPT_REGW))
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@ -420,7 +420,7 @@ ALT(DEF_ASM_OP2(cmovo, 0x0f40, 0, OPC_MODRM | OPC_TEST | OPC_WLX, OPT_REGW | OPT
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/* movd shouldn't accept REG64, but AMD64 spec uses it for 32 and 64 bit
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moves, so let's be compatible. */
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ALT(DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA | OPT_REG64, OPT_MMXSSE ))
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ALT(DEF_ASM_OP2(movq, 0x480f6e, 0, OPC_MODRM, OPT_REG64, OPT_MMXSSE ))
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ALT(DEF_ASM_OP2(movq, 0x0f6e, 0, OPC_MODRM | OPC_48, OPT_REG64, OPT_MMXSSE ))
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ALT(DEF_ASM_OP2(movq, 0x0f6f, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX ))
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ALT(DEF_ASM_OP2(movd, 0x0f7e, 0, OPC_MODRM, OPT_MMXSSE, OPT_EA | OPT_REG32 ))
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ALT(DEF_ASM_OP2(movd, 0x0f7e, 0, OPC_MODRM, OPT_MMXSSE, OPT_EA | OPT_REG64 ))
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