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riscv64-asm: Add lui, auipc
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@ -179,6 +179,49 @@ static void asm_unary_opcode(TCCState *s1, int token)
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}
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}
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static void asm_emit_u(int token, uint32_t opcode, const Operand* rd, const Operand* rs2)
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{
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if (rd->type != OP_REG) {
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tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
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return;
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}
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if (rs2->type != OP_IM12S && rs2->type != OP_IM32) {
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tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token, NULL));
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return;
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} else if (rs2->e.v >= 0x100000) {
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tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0xfffff", get_tok_str(token, NULL));
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return;
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}
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/* U-type instruction:
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31...12 imm[31:12]
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11...7 rd
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6...0 opcode */
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gen_le32(opcode | ENCODE_RD(rd->reg) | (rs2->e.v << 12));
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}
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static void asm_binary_opcode(TCCState* s1, int token)
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{
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Operand ops[2];
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parse_operand(s1, &ops[0]);
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if (tok == ',')
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next();
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else
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expect("','");
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parse_operand(s1, &ops[1]);
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switch (token) {
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case TOK_ASM_lui:
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asm_emit_u(token, (0xD << 2) | 3, &ops[0], &ops[1]);
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return;
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case TOK_ASM_auipc:
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asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[1]);
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return;
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default:
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expect("binary instruction");
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}
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}
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ST_FUNC void asm_opcode(TCCState *s1, int token)
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{
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switch (token) {
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@ -204,6 +247,11 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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asm_unary_opcode(s1, token);
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return;
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case TOK_ASM_lui:
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case TOK_ASM_auipc:
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asm_binary_opcode(s1, token);
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return;
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default:
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expect("known instruction");
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}
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@ -82,6 +82,11 @@
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#define DEF_ASM_WITH_SUFFIX(x, y) \
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DEF(TOK_ASM_ ## x ## _ ## y, #x #y)
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/* Arithmetic */
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DEF_ASM(lui)
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DEF_ASM(auipc)
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/* Sync */
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DEF_ASM(fence)
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