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arm-asm: Add cdp
Also add p0...p15 (coprocessors), c0...c15 (coprocessor register aliases)
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parent
593bed9b52
commit
036a7fe7d4
77
arm-asm.c
77
arm-asm.c
@ -165,6 +165,26 @@ static void asm_emit_opcode(int token, uint32_t opcode) {
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gen_le32((condition_code_of_token(token) << 28) | opcode);
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}
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static void asm_emit_coprocessor_opcode(uint32_t high_nibble, uint8_t cp_number, uint8_t cp_opcode, uint8_t cp_destination_register, uint8_t cp_n_operand_register, uint8_t cp_m_operand_register, uint8_t cp_opcode2, int inter_processor_transfer)
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{
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uint32_t opcode = 0xe000000;
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if (inter_processor_transfer)
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opcode |= 1 << 4;
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//assert(cp_opcode < 16);
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opcode |= cp_opcode << 20;
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//assert(cp_n_operand_register < 16);
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opcode |= cp_n_operand_register << 16;
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//assert(cp_destination_register < 16);
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opcode |= cp_destination_register << 12;
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//assert(cp_number < 16);
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opcode |= cp_number << 8;
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//assert(cp_information < 8);
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opcode |= cp_opcode2 << 5;
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//assert(cp_m_operand_register < 16);
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opcode |= cp_m_operand_register;
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gen_le32((high_nibble << 28) | opcode);
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}
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static void asm_nullary_opcode(int token)
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{
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switch (ARM_INSTRUCTION_GROUP(token)) {
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@ -309,6 +329,60 @@ static void asm_binary_opcode(TCCState *s1, int token)
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}
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}
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static void asm_coprocessor_opcode(TCCState *s1, int token) {
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uint8_t coprocessor;
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Operand opcode1;
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Operand opcode2;
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uint8_t registers[3];
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unsigned int i;
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if (tok >= TOK_ASM_p0 && tok <= TOK_ASM_p15) {
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coprocessor = tok - TOK_ASM_p0;
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next();
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} else {
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expect("'p<number>'");
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return;
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}
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if (tok == ',')
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next();
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else
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expect("','");
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parse_operand(s1, &opcode1);
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if (opcode1.type != OP_IM8 || opcode1.e.v > 15) {
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tcc_error("opcode1 of instruction '%s' must be an immediate value between 0 and 15", get_tok_str(token, NULL));
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return;
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}
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for (i = 0; i < 3; ++i) {
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if (tok == ',')
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next();
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else
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expect("','");
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if (tok >= TOK_ASM_c0 && tok <= TOK_ASM_c15) {
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registers[i] = tok - TOK_ASM_c0;
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next();
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} else {
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expect("'c<number>");
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return;
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}
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}
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if (tok == ',') {
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next();
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parse_operand(s1, &opcode2);
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} else {
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opcode2.type = OP_IM8;
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opcode2.e.v = 0;
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}
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if (opcode2.type != OP_IM8 || opcode2.e.v > 15) {
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tcc_error("opcode2 of instruction '%s' must be an immediate value between 0 and 15", get_tok_str(token, NULL));
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return;
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}
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asm_emit_coprocessor_opcode(condition_code_of_token(token), coprocessor, opcode1.e.v, registers[0], registers[1], registers[2], opcode2.e.v, 0);
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}
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/* data processing and single data transfer instructions only */
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#define ENCODE_RN(register_index) ((register_index) << 16)
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#define ENCODE_RD(register_index) ((register_index) << 12)
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@ -1468,6 +1542,9 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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case TOK_ASM_umlaleq:
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case TOK_ASM_umlalseq:
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return asm_long_multiplication_opcode(s1, token);
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case TOK_ASM_cdpeq:
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return asm_coprocessor_opcode(s1, token);
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default:
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expect("known instruction");
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}
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40
arm-tok.h
40
arm-tok.h
@ -28,6 +28,44 @@
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DEF_ASM(lr) /* alias for r14 */
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DEF_ASM(pc) /* alias for r15 */
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/* coprocessors */
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DEF_ASM(p0)
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DEF_ASM(p1)
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DEF_ASM(p2)
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DEF_ASM(p3)
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DEF_ASM(p4)
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DEF_ASM(p5)
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DEF_ASM(p6)
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DEF_ASM(p7)
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DEF_ASM(p8)
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DEF_ASM(p9)
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DEF_ASM(p10)
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DEF_ASM(p11)
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DEF_ASM(p12)
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DEF_ASM(p13)
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DEF_ASM(p14)
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DEF_ASM(p15)
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/* coprocessor registers */
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DEF_ASM(c0)
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DEF_ASM(c1)
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DEF_ASM(c2)
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DEF_ASM(c3)
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DEF_ASM(c4)
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DEF_ASM(c5)
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DEF_ASM(c6)
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DEF_ASM(c7)
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DEF_ASM(c8)
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DEF_ASM(c9)
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DEF_ASM(c10)
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DEF_ASM(c11)
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DEF_ASM(c12)
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DEF_ASM(c13)
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DEF_ASM(c14)
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DEF_ASM(c15)
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/* data processing directives */
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DEF_ASM(asl)
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@ -170,3 +208,5 @@
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DEF_ASM_CONDED(rors)
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DEF_ASM_CONDED(rrx)
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DEF_ASM_CONDED(rrxs)
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DEF_ASM_CONDED(cdp)
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@ -89,6 +89,7 @@ do
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"r4, #0x0201" \
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"r4, #0xFFFFFF00" \
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"r2, #-4" \
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"p10, #7, c2, c0, c1, #4" \
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"#4" \
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"#-4" \
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""
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