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arm-asm: Implement ldr and str with shifted register offset
Factor out asm_parse_optional_shift
This commit is contained in:
Danny Milosavljevic
parent
1d7b233562
commit
007839597f
102
arm-asm.c
102
arm-asm.c
@ -433,6 +433,50 @@ static void asm_block_data_transfer_opcode(TCCState *s1, int token)
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}
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}
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/* Parses shift directive and returns the parts that would have to be set in the opcode because of it.
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Does not encode the actual shift amount.
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It's not an error if there is no shift directive.
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NB_SHIFT: will be set to 1 iff SHIFT is filled. Note that for rrx, there's no need to fill SHIFT.
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SHIFT: will be filled in with the shift operand to use, if any. */
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static uint32_t asm_parse_optional_shift(TCCState* s1, int* nb_shift, Operand* shift)
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{
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uint32_t opcode = 0;
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*nb_shift = 0;
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switch (tok) {
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case TOK_ASM_asl:
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case TOK_ASM_lsl:
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case TOK_ASM_asr:
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case TOK_ASM_lsr:
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case TOK_ASM_ror:
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switch (tok) {
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case TOK_ASM_asl:
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/* fallthrough */
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case TOK_ASM_lsl:
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opcode = ENCODE_BARREL_SHIFTER_MODE_LSL;
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break;
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case TOK_ASM_asr:
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opcode = ENCODE_BARREL_SHIFTER_MODE_ASR;
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break;
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case TOK_ASM_lsr:
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opcode = ENCODE_BARREL_SHIFTER_MODE_LSR;
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break;
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case TOK_ASM_ror:
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opcode = ENCODE_BARREL_SHIFTER_MODE_ROR;
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break;
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}
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next();
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parse_operand(s1, shift);
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*nb_shift = 1;
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break;
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case TOK_ASM_rrx:
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next();
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opcode = ENCODE_BARREL_SHIFTER_MODE_ROR;
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break;
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}
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return opcode;
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}
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static uint32_t asm_encode_shift(Operand* shift)
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{
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uint64_t amount;
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@ -482,37 +526,7 @@ static void asm_data_processing_opcode(TCCState *s1, int token)
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}
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if (tok == ',')
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next();
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switch (tok) {
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case TOK_ASM_asl:
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case TOK_ASM_lsl:
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case TOK_ASM_asr:
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case TOK_ASM_lsr:
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case TOK_ASM_ror:
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switch (tok) {
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case TOK_ASM_asl:
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/* fallthrough */
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case TOK_ASM_lsl:
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operands |= ENCODE_BARREL_SHIFTER_MODE_LSL;
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break;
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case TOK_ASM_asr:
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operands |= ENCODE_BARREL_SHIFTER_MODE_ASR;
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break;
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case TOK_ASM_lsr:
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operands |= ENCODE_BARREL_SHIFTER_MODE_LSR;
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break;
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case TOK_ASM_ror:
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operands |= ENCODE_BARREL_SHIFTER_MODE_ROR;
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break;
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}
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next();
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parse_operand(s1, &shift);
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nb_shift = 1;
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break;
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case TOK_ASM_rrx:
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next();
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operands |= ENCODE_BARREL_SHIFTER_MODE_ROR;
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break;
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}
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operands |= asm_parse_optional_shift(s1, &nb_shift, &shift);
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if (nb_ops < 2)
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expect("at least two operands");
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else if (nb_ops == 2) {
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@ -940,6 +954,8 @@ static void asm_single_data_transfer_opcode(TCCState *s1, int token)
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{
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Operand ops[3];
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Operand strex_operand;
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Operand shift;
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int nb_shift = 0;
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int exclam = 0;
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int closed_bracket = 0;
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int op2_minus = 0;
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@ -999,6 +1015,14 @@ static void asm_single_data_transfer_opcode(TCCState *s1, int token)
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next();
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}
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parse_operand(s1, &ops[2]);
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if (ops[2].type == OP_REG32) {
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if (tok == ',') {
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next();
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opcode |= asm_parse_optional_shift(s1, &nb_shift, &shift);
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if (opcode == 0)
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expect("shift directive, or no comma");
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}
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}
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} else {
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// end of input expression in brackets--assume 0 offset
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ops[2].type = OP_IM8;
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@ -1061,6 +1085,8 @@ static void asm_single_data_transfer_opcode(TCCState *s1, int token)
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/* fallthrough */
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case TOK_ASM_streq:
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opcode |= 1 << 26; // Load/Store
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if (nb_shift)
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opcode |= asm_encode_shift(&shift);
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asm_emit_opcode(token, opcode);
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break;
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case TOK_ASM_ldrbeq:
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@ -1069,14 +1095,16 @@ static void asm_single_data_transfer_opcode(TCCState *s1, int token)
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case TOK_ASM_ldreq:
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opcode |= 1 << 20; // L
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opcode |= 1 << 26; // Load/Store
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if (nb_shift)
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opcode |= asm_encode_shift(&shift);
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asm_emit_opcode(token, opcode);
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break;
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case TOK_ASM_strexbeq:
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opcode |= 1 << 22; // B
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/* fallthrough */
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case TOK_ASM_strexeq:
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if (opcode & 0xFFF) {
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tcc_error("offset not allowed with 'strex'");
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if ((opcode & 0xFFF) || nb_shift) {
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tcc_error("neither offset nor shift allowed with 'strex'");
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return;
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} else if (opcode & ENCODE_IMMEDIATE_FLAG) { // if set, it means it's NOT immediate
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tcc_error("offset not allowed with 'strex'");
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@ -1087,7 +1115,7 @@ static void asm_single_data_transfer_opcode(TCCState *s1, int token)
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return;
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}
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opcode |= 0xf90;
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opcode |= 0xf90; // Used to mean: barrel shifter is enabled, barrel shift register is r15, mode is LSL
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opcode |= strex_operand.reg;
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asm_emit_opcode(token, opcode);
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break;
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@ -1095,8 +1123,8 @@ static void asm_single_data_transfer_opcode(TCCState *s1, int token)
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opcode |= 1 << 22; // B
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/* fallthrough */
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case TOK_ASM_ldrexeq:
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if (opcode & 0xFFF) {
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tcc_error("offset not allowed with 'ldrex'");
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if ((opcode & 0xFFF) || nb_shift) {
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tcc_error("neither offset nor shift allowed with 'ldrex'");
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return;
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} else if (opcode & ENCODE_IMMEDIATE_FLAG) { // if set, it means it's NOT immediate
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tcc_error("offset not allowed with 'ldrex'");
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@ -1108,7 +1136,7 @@ static void asm_single_data_transfer_opcode(TCCState *s1, int token)
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}
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opcode |= 1 << 20; // L
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opcode |= 0x00f;
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opcode |= 0xf90;
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opcode |= 0xf90; // Used to mean: barrel shifter is enabled, barrel shift register is r15, mode is LSL
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asm_emit_opcode(token, opcode);
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break;
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default:
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@ -61,6 +61,17 @@ do
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"r2, [r3, -r4]" \
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"r2, [r3, -r4]!" \
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"r2, [r3], r4" \
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"r2, [r3], -r4" \
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"r2, [r3]" \
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"r2, r3, [r4, lsl# 2]" \
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"r2, [r3, r4, lsr# 1]" \
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"r2, [r3, r4, lsr# 2]!" \
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"r2, [r3, -r4, ror# 3]" \
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"r2, [r3, -r4, lsl# 1]!" \
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"r2, [r3], r4, lsl# 3" \
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"r2, [r3], -r4, asr# 31" \
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"r2, [r3], -r4, asl# 1" \
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"r2, [r3], -r4, rrx" \
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"r2, [r3]" \
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"r2, r3, [r4]" \
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"r2, [r3, #4]" \
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