2021-04-06 18:43:21 +08:00
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/* ------------------------------------------------------------------ */
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/* WARNING: relative order of tokens is important. */
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// See https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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/* register */
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DEF_ASM(x0)
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DEF_ASM(x1)
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DEF_ASM(x2)
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DEF_ASM(x3)
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DEF_ASM(x4)
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DEF_ASM(x5)
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DEF_ASM(x6)
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DEF_ASM(x7)
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DEF_ASM(x8)
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DEF_ASM(x9)
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DEF_ASM(x10)
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DEF_ASM(x11)
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DEF_ASM(x12)
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DEF_ASM(x13)
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DEF_ASM(x14)
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DEF_ASM(x15)
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DEF_ASM(x16)
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DEF_ASM(x17)
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DEF_ASM(x18)
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DEF_ASM(x19)
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DEF_ASM(x20)
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DEF_ASM(x21)
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DEF_ASM(x22)
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DEF_ASM(x23)
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DEF_ASM(x24)
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DEF_ASM(x25)
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DEF_ASM(x26)
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DEF_ASM(x27)
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DEF_ASM(x28)
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DEF_ASM(x29)
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DEF_ASM(x30)
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DEF_ASM(x31)
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/* register macros */
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DEF_ASM(zero)
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DEF_ASM(ra)
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DEF_ASM(sp)
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DEF_ASM(gp)
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DEF_ASM(tp)
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DEF_ASM(t0)
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DEF_ASM(t1)
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DEF_ASM(t2)
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DEF_ASM(fp)
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DEF_ASM(s1)
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DEF_ASM(a0)
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DEF_ASM(a1)
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DEF_ASM(a2)
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DEF_ASM(a3)
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DEF_ASM(a4)
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DEF_ASM(a5)
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DEF_ASM(a6)
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DEF_ASM(a7)
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DEF_ASM(s2)
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DEF_ASM(s3)
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DEF_ASM(s4)
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DEF_ASM(s5)
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DEF_ASM(s6)
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DEF_ASM(s7)
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DEF_ASM(s8)
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DEF_ASM(s9)
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DEF_ASM(s10)
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DEF_ASM(s11)
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DEF_ASM(t3)
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DEF_ASM(t4)
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DEF_ASM(t5)
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DEF_ASM(t6)
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DEF_ASM(s0) // = x8
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DEF_ASM(pc)
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#define DEF_ASM_WITH_SUFFIX(x, y) \
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DEF(TOK_ASM_ ## x ## _ ## y, #x #y)
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riscv64-asm: Add lb, lh, lw, lbu, lhu, ld, lwu, sb, sh, sw, sd
2021-04-06 19:32:29 +08:00
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/* Loads */
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DEF_ASM(lb)
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DEF_ASM(lh)
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DEF_ASM(lw)
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DEF_ASM(lbu)
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DEF_ASM(lhu)
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DEF_ASM(ld)
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DEF_ASM(lq)
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DEF_ASM(lwu)
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DEF_ASM(ldu)
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/* Stores */
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DEF_ASM(sb)
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DEF_ASM(sh)
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DEF_ASM(sw)
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DEF_ASM(sd)
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DEF_ASM(sq)
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riscv64-asm: Add sll, slli, srl, srli, sra, srai, sllw, slld, slliw, sllid, srlw, srld, srliw, srlid, sraw, srad, sraiw, sraid
2021-04-06 19:22:08 +08:00
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/* Shifts */
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DEF_ASM(sll)
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DEF_ASM(slli)
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DEF_ASM(srl)
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DEF_ASM(srli)
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DEF_ASM(sra)
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DEF_ASM(srai)
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DEF_ASM(sllw)
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DEF_ASM(slld)
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DEF_ASM(slliw)
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DEF_ASM(sllid)
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DEF_ASM(srlw)
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DEF_ASM(srld)
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DEF_ASM(srliw)
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DEF_ASM(srlid)
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DEF_ASM(sraw)
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DEF_ASM(srad)
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DEF_ASM(sraiw)
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DEF_ASM(sraid)
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2021-04-06 19:13:52 +08:00
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/* Arithmetic */
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riscv64-asm: Add add, addi, sub, addw, addd, addiw, addid, subw, subd, xor, xori, or, ori, and, andi, slt, slti, sltu, sltiu
2021-04-06 19:26:09 +08:00
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DEF_ASM(add)
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DEF_ASM(addi)
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DEF_ASM(sub)
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2021-04-06 19:13:52 +08:00
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DEF_ASM(lui)
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DEF_ASM(auipc)
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riscv64-asm: Add add, addi, sub, addw, addd, addiw, addid, subw, subd, xor, xori, or, ori, and, andi, slt, slti, sltu, sltiu
2021-04-06 19:26:09 +08:00
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DEF_ASM(addw)
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DEF_ASM(addd)
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DEF_ASM(addiw)
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DEF_ASM(addid)
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DEF_ASM(subw)
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DEF_ASM(subd)
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/* Logical */
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DEF_ASM(xor)
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DEF_ASM(xori)
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DEF_ASM(or)
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DEF_ASM(ori)
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DEF_ASM(and)
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DEF_ASM(andi)
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/* Compare */
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DEF_ASM(slt)
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DEF_ASM(slti)
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DEF_ASM(sltu)
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DEF_ASM(sltiu)
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2021-04-06 19:36:33 +08:00
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/* Branch */
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DEF_ASM(beq)
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DEF_ASM(bne)
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DEF_ASM(blt)
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DEF_ASM(bge)
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DEF_ASM(bltu)
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DEF_ASM(bgeu)
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2021-04-06 18:43:21 +08:00
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/* Sync */
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DEF_ASM(fence)
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DEF_ASM_WITH_SUFFIX(fence, i)
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/* System call */
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DEF_ASM(scall)
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DEF_ASM(sbreak)
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2021-04-06 18:51:18 +08:00
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/* Counters */
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DEF_ASM(rdcycle)
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DEF_ASM(rdcycleh)
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DEF_ASM(rdtime)
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DEF_ASM(rdtimeh)
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DEF_ASM(rdinstret)
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DEF_ASM(rdinstreth)
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2021-04-06 18:43:21 +08:00
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/* Privileged Instructions */
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DEF_ASM(ecall)
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DEF_ASM(ebreak)
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DEF_ASM(mrts)
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DEF_ASM(mrth)
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DEF_ASM(hrts)
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DEF_ASM(wfi)
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