This file documents the GNU Make utility, which determines automatically which pieces of a large program need to be recompiled, and issues the commands to recompile them.

This is Edition 0.47 DRAFT, last updated 1 November 1994, of The GNU Make Manual, for make, Version 3.72 Beta.

Copyright (C) 1988, '89, '90, '91, '92, '93, '94 Free Software Foundation, Inc.

Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies.

Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one.

Permission is granted to copy and distribute translations of this manual into another language, under the above conditions for modified versions, except that this permission notice may be stated in a translation approved by the Free Software Foundation.

Make
****

The GNU make utility automatically determines which pieces of a large program need to be recompiled, and issues the commands to recompile them.

This is Edition 0.47 DRAFT of the GNU Make Manual, last updated 1 November 1994 for make Version 3.72 Beta.

This manual describes make and contains the following chapters:

Overview of make
****************

The make utility automatically determines which pieces of a large program need to be recompiled, and issues commands to recompile them. This manual describes GNU make, which was implemented by Richard Stallman and Roland McGrath.  GNU make conforms to section 6.2 of IEEE Standard 1003.2-1992 (POSIX.2).

Our examples show C programs, since they are most common, but you can use make with any programming language whose compiler can be run with a shell command.  Indeed, make is not limited to programs.  You can use it to describe any task where some files must be updated automatically from others whenever the others change.

Preparing and Running Make
==========================

To prepare to use make, you must write a file called the makefile that describes the relationships among files in your program and provides commands for updating each file. In a program, typically, the executable file is updated from object files, which are in turn made by compiling source files.

Once a suitable makefile exists, each time you change some source files, this simple shell command:

     make

suffices to perform all necessary recompilations.  The make program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated.  For each of those files, it issues the commands recorded in the data base.

You can provide command line arguments to make to control which files should be recompiled, or how.  See How to Run make.

How to Read This Manual
=======================

If you are new to make, or are looking for a general introduction, read the first few sections of each chapter, skipping the later sections.  In each chapter, the first few sections contain introductory or general information and the later sections contain specialized or technical information. The exception is the second chapter, An Introduction to Makefiles, all of which is introductory.

If you are familiar with other make programs, see Features of GNU make, which lists the enhancements GNU make has, and Incompatibilities and Missing Features, which explains the few things GNU make lacks that others have.

For a quick summary, see Options Summary, Quick Reference, and Special Targets.

Problems and Bugs
=================

If you have problems with GNU make or think you've found a bug, please report it to the developers; we cannot promise to do anything but we might well want to fix it.

Before reporting a bug, make sure you've actually found a real bug. Carefully reread the documentation and see if it really says you can do what you're trying to do.  If it's not clear whether you should be able to do something or not, report that too; it's a bug in the documentation!

Before reporting a bug or trying to fix it yourself, try to isolate it to the smallest possible makefile that reproduces the problem.  Then send us the makefile and the exact results make gave you.  Also say what you expected to occur; this will help us decide whether the problem was really in the documentation.

Once you've got a precise problem, please send electronic mail either through the Internet or via UUCP:

     Internet address:
         bug-gnu-utils@prep.ai.mit.edu

     UUCP path:
         mit-eddie!prep.ai.mit.edu!bug-gnu-utils

Please include the version number of make you are using.  You can get this information with the command make --version. Be sure also to include the type of machine and operating system you are using.  If possible, include the contents of the file config.h that is generated by the configuration process.

Non-bug suggestions are always welcome as well.  If you have questions about things that are unclear in the documentation or are just obscure features, send a message to the bug reporting address.  We cannot guarantee you'll get help with your problem, but many seasoned make users read the mailing list and they will probably try to help you out.  The maintainers sometimes answer such questions as well, when time permits.

An Introduction to Makefiles
****************************

You need a file called a makefile to tell make what to do. Most often, the makefile tells make how to compile and link a program.

In this chapter, we will discuss a simple makefile that describes how to compile and link a text editor which consists of eight C source files and three header files.  The makefile can also tell make how to run miscellaneous commands when explicitly asked (for example, to remove certain files as a clean-up operation).  To see a more complex example of a makefile, see Complex Makefile.

When make recompiles the editor, each changed C source file must be recompiled.  If a header file has changed, each C source file that includes the header file must be recompiled to be safe.  Each compilation produces an object file corresponding to the source file. Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable editor.

What a Rule Looks Like
======================

A simple makefile consists of ``rules'' with the following shape:

     TARGET ... : DEPENDENCIES ...
             COMMAND
             ...
             ...

A target is usually the name of a file that is generated by a program; examples of targets are executable or object files.  A target can also be the name of an action to carry out, such as clean (see Phony Targets).

A dependency is a file that is used as input to create the target.  A target often depends on several files.

A command is an action that make carries out. A rule may have more than one command, each on its own line. Please note: you need to put a tab character at the beginning of every command line!  This is an obscurity that catches the unwary.

Usually a command is in a rule with dependencies and serves to create a target file if any of the dependencies change.  However, the rule that specifies commands for the target need not have dependencies.  For example, the rule containing the delete command associated with the target clean does not have dependencies.

A rule, then, explains how and when to remake certain files which are the targets of the particular rule.  make carries out the commands on the dependencies to create or update the target.  A rule can also explain how and when to carry out an action. See Writing Rules.

A makefile may contain other text besides rules, but a simple makefile need only contain rules.  Rules may look somewhat more complicated than shown in this template, but all fit the pattern more or less.

A Simple Makefile
=================

Here is a straightforward makefile that describes the way an executable file called edit depends on eight object files which, in turn, depend on eight C source and three header files.

In this example, all the C files include defs.h, but only those defining editing commands include command.h, and only low level files that change the editor buffer include buffer.h.

     edit : main.o kbd.o command.o display.o \
            insert.o search.o files.o utils.o
             cc -o edit main.o kbd.o command.o display.o \
                        insert.o search.o files.o utils.o

     main.o : main.c defs.h
             cc -c main.c
     kbd.o : kbd.c defs.h command.h
             cc -c kbd.c
     command.o : command.c defs.h command.h
             cc -c command.c
     display.o : display.c defs.h buffer.h
             cc -c display.c
     insert.o : insert.c defs.h buffer.h
             cc -c insert.c
     search.o : search.c defs.h buffer.h
             cc -c search.c
     files.o : files.c defs.h buffer.h command.h
             cc -c files.c
     utils.o : utils.c defs.h
             cc -c utils.c
     clean :
             rm edit main.o kbd.o command.o display.o \
                insert.o search.o files.o utils.o

We split each long line into two lines using backslash-newline; this is like using one long line, but is easier to read.

To use this makefile to create the executable file called edit, type:

     make

To use this makefile to delete the executable file and all the object files from the directory, type:

     make clean

In the example makefile, the targets include the executable file edit, and the object files main.o and kbd.o.  The dependencies are files such as main.c and defs.h. In fact, each .o file is both a target and a dependency. Commands include cc -c main.c and cc -c kbd.c.

When a target is a file, it needs to be recompiled or relinked if any of its dependencies change.  In addition, any dependencies that are themselves automatically generated should be updated first.  In this example, edit depends on each of the eight object files; the object file main.o depends on the source file main.c and on the header file defs.h.

A shell command follows each line that contains a target and dependencies.  These shell commands say how to update the target file. A tab character must come at the beginning of every command line to distinguish commands lines from other lines in the makefile.  (Bear in mind that make does not know anything about how the commands work.  It is up to you to supply commands that will update the target file properly.  All make does is execute the commands in the rule you have specified when the target file needs to be updated.)

The target clean is not a file, but merely the name of an action.  Since you normally do not want to carry out the actions in this rule, clean is not a dependency of any other rule. Consequently, make never does anything with it unless you tell it specifically.  Note that this rule not only is not a dependency, it also does not have any dependencies, so the only purpose of the rule is to run the specified commands.  Targets that do not refer to files but are just actions are called phony targets.  See Phony Targets, for information about this kind of target.  See Errors in Commands, to see how to cause make to ignore errors from rm or any other command.

How make Processes a Makefile
=============================

By default, make starts with the first rule (not counting rules whose target names start with .).  This is called the default goal.  (Goals are the targets that make strives ultimately to update.  See Arguments to Specify the Goals.)

In the simple example of the previous section, the default goal is to update the executable program edit; therefore, we put that rule first.

Thus, when you give the command:

     make

make reads the makefile in the current directory and begins by processing the first rule.  In the example, this rule is for relinking edit; but before make can fully process this rule, it must process the rules for the files that edit depends on, which in this case are the object files.  Each of these files is processed according to its own rule.  These rules say to update each .o file by compiling its source file.  The recompilation must be done if the source file, or any of the header files named as dependencies, is more recent than the object file, or if the object file does not exist.

The other rules are processed because their targets appear as dependencies of the goal.  If some other rule is not depended on by the goal (or anything it depends on, etc.), that rule is not processed, unless you tell make to do so (with a command such as make clean).

Before recompiling an object file, make considers updating its dependencies, the source file and header files.  This makefile does not specify anything to be done for them---the .c and .h files are not the targets of any rules---so make does nothing for these files.  But make would update automatically generated C programs, such as those made by Bison or Yacc, by their own rules at this time.

After recompiling whichever object files need it, make decides whether to relink edit.  This must be done if the file edit does not exist, or if any of the object files are newer than it.  If an object file was just recompiled, it is now newer than edit, so edit is relinked.

Thus, if we change the file insert.c and run make, make will compile that file to update insert.o, and then link edit.  If we change the file command.h and run make, make will recompile the object files kbd.o, command.o and files.o and then link the file edit.

Variables Make Makefiles Simpler
================================

In our example, we had to list all the object files twice in the rule for edit (repeated here):

     edit : main.o kbd.o command.o display.o \
                   insert.o search.o files.o utils.o
             cc -o edit main.o kbd.o command.o display.o \
                        insert.o search.o files.o utils.o

Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other.  We can eliminate the risk and simplify the makefile by using a variable.  Variables allow a text string to be defined once and substituted in multiple places later (see How to Use Variables).

It is standard practice for every makefile to have a variable named objects, OBJECTS, objs, OBJS, obj, or OBJ which is a list of all object file names.  We would define such a variable objects with a line like this in the makefile:

     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o

Then, each place we want to put a list of the object file names, we can substitute the variable's value by writing $(objects) (see How to Use Variables).

Here is how the complete simple makefile looks when you use a variable for the object files:

     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o

     edit : $(objects)
             cc -o edit $(objects)
     main.o : main.c defs.h
             cc -c main.c
     kbd.o : kbd.c defs.h command.h
             cc -c kbd.c
     command.o : command.c defs.h command.h
             cc -c command.c
     display.o : display.c defs.h buffer.h
             cc -c display.c
     insert.o : insert.c defs.h buffer.h
             cc -c insert.c
     search.o : search.c defs.h buffer.h
             cc -c search.c
     files.o : files.c defs.h buffer.h command.h
             cc -c files.c
     utils.o : utils.c defs.h
             cc -c utils.c
     clean :
             rm edit $(objects)

Letting make Deduce the Commands
================================

It is not necessary to spell out the commands for compiling the individual C source files, because make can figure them out: it has an implicit rule for updating a .o file from a correspondingly named .c file using a cc -c command.  For example, it will use the command cc -c main.c -o main.o to compile main.c into main.o.  We can therefore omit the commands from the rules for the object files.  See Using Implicit Rules.

When a .c file is used automatically in this way, it is also automatically added to the list of dependencies.  We can therefore omit the .c files from the dependencies, provided we omit the commands.

Here is the entire example, with both of these changes, and a variable objects as suggested above:

     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o

     edit : $(objects)
             cc -o edit $(objects)

     main.o : defs.h
     kbd.o : defs.h command.h
     command.o : defs.h command.h
     display.o : defs.h buffer.h
     insert.o : defs.h buffer.h
     search.o : defs.h buffer.h
     files.o : defs.h buffer.h command.h
     utils.o : defs.h

     .PHONY : clean
     clean :
             -rm edit $(objects)

This is how we would write the makefile in actual practice.  (The complications associated with clean are described elsewhere. See Phony Targets, and Errors in Commands.)

Because implicit rules are so convenient, they are important.  You will see them used frequently.

Another Style of Makefile
=========================

When the objects of a makefile are created only by implicit rules, an alternative style of makefile is possible.  In this style of makefile, you group entries by their dependencies instead of by their targets. Here is what one looks like:

     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o

     edit : $(objects)
             cc -o edit $(objects)

     $(objects) : defs.h
     kbd.o command.o files.o : command.h
     display.o insert.o search.o files.o : buffer.h

Here defs.h is given as a dependency of all the object files; command.h and buffer.h are dependencies of the specific object files listed for them.

Whether this is better is a matter of taste: it is more compact, but some people dislike it because they find it clearer to put all the information about each target in one place.

Rules for Cleaning the Directory
================================

Compiling a program is not the only thing you might want to write rules for.  Makefiles commonly tell how to do a few other things besides compiling a program: for example, how to delete all the object files and executables so that the directory is clean.

Here is how we could write a make rule for cleaning our example editor:

     clean:
             rm edit $(objects)

In practice, we might want to write the rule in a somewhat more complicated manner to handle unanticipated situations.  We would do this:

     .PHONY : clean
     clean :
             -rm edit $(objects)

This prevents make from getting confused by an actual file called clean and causes it to continue in spite of errors from rm.  (See Phony Targets, and Errors in Commands.)

A rule such as this should not be placed at the beginning of the makefile, because we do not want it to run by default!  Thus, in the example makefile, we want the rule for edit, which recompiles the editor, to remain the default goal.

Since clean is not a dependency of edit, this rule will not run at all if we give the command make with no arguments.  In order to make the rule run, we have to type make clean. See How to Run make.

Writing Makefiles
*****************

The information that tells make how to recompile a system comes from reading a data base called the makefile.

What Makefiles Contain
======================

Makefiles contain five kinds of things: explicit rules, implicit rules, variable definitions, directives, and comments.  Rules, variables, and directives are described at length in later chapters.

  * An explicit rule says when and how to remake one or more files, called the rule's targets.  It lists the other files that the targets depend on, and may also give commands to use to create or update the targets.  See Writing Rules.

  * An implicit rule says when and how to remake a class of files based on their names.  It describes how a target may depend on a file with a name similar to the target and gives commands to create or update such a target.  See Using Implicit Rules.

  * A variable definition is a line that specifies a text string value for a variable that can be substituted into the text later.  The simple makefile example shows a variable definition for objects as a list of all object files (see Variables Make Makefiles Simpler).

  * A directive is a command for make to do something special while reading the makefile.  These include:

       * Reading another makefile (see Including Other Makefiles).

       * Deciding (based on the values of variables) whether to use or ignore a part of the makefile (see Conditional Parts of Makefiles).

       * Defining a variable from a verbatim string containing multiple lines (see Defining Variables Verbatim).

  * # in a line of a makefile starts a comment.  It and the rest of the line are ignored, except that a trailing backslash not escaped by another backslash will continue the comment across multiple lines. Comments may appear on any of the lines in the makefile, except within a define directive, and perhaps within commands (where the shell decides what is a comment).  A line containing just a comment (with perhaps spaces before it) is effectively blank, and is ignored.

What Name to Give Your Makefile
===============================

By default, when make looks for the makefile, it tries the following names, in order: GNUmakefile, makefile and Makefile.

Normally you should call your makefile either makefile or Makefile.  (We recommend Makefile because it appears prominently near the beginning of a directory listing, right near other important files such as README.)  The first name checked, GNUmakefile, is not recommended for most makefiles.  You should use this name if you have a makefile that is specific to GNU make, and will not be understood by other versions of make.  Other make programs look for makefile and Makefile, but not GNUmakefile.

If make finds none of these names, it does not use any makefile. Then you must specify a goal with a command argument, and make will attempt to figure out how to remake it using only its built-in implicit rules.  See Using Implicit Rules.

If you want to use a nonstandard name for your makefile, you can specify the makefile name with the -f or --file option.  The arguments -f NAME or --file=NAME tell make to read the file NAME as the makefile.  If you use more than one -f or --file option, you can specify several makefiles.  All the makefiles are effectively concatenated in the order specified.  The default makefile names GNUmakefile, makefile and Makefile are not checked automatically if you specify -f or --file.

Including Other Makefiles
=========================

The include directive tells make to suspend reading the current makefile and read one or more other makefiles before continuing. The directive is a line in the makefile that looks like this:

     include FILENAMES...

FILENAMES can contain shell file name patterns.

Extra spaces are allowed and ignored at the beginning of the line, but a tab is not allowed.  (If the line begins with a tab, it will be considered a command line.)  Whitespace is required between include and the file names, and between file names; extra whitespace is ignored there and at the end of the directive.  A comment starting with # is allowed at the end of the line.  If the file names contain any variable or function references, they are expanded.  See How to Use Variables.

For example, if you have three .mk files, a.mk, b.mk, and c.mk, and $(bar) expands to bish bash, then the following expression

     include foo *.mk $(bar)

is equivalent to

     include foo a.mk b.mk c.mk bish bash

When make processes an include directive, it suspends reading of the containing makefile and reads from each listed file in turn.  When that is finished, make resumes reading the makefile in which the directive appears.

One occasion for using include directives is when several programs, handled by individual makefiles in various directories, need to use a common set of variable definitions (see Setting Variables) or pattern rules (see Defining and Redefining Pattern Rules).

Another such occasion is when you want to generate dependencies from source files automatically; the dependencies can be put in a file that is included by the main makefile.  This practice is generally cleaner than that of somehow appending the dependencies to the end of the main makefile as has been traditionally done with other versions of make.  See Automatic Dependencies.

If the specified name does not start with a slash, and the file is not found in the current directory, several other directories are searched. First, any directories you have specified with the -I or --include-dir option are searched (see Summary of Options). Then the following directories (if they exist) are searched, in this order: PREFIX/include (normally /usr/local/include) /usr/gnu/include, /usr/local/include, /usr/include.

If an included makefile cannot be found in any of these directories, a warning message is generated, but it is not an immediately fatal error; processing of the makefile containing the include continues. Once it has finished reading makefiles, make will try to remake any that are out of date or don't exist. See How Makefiles Are Remade. Only after it has tried to find a way to remake a makefile and failed, will make diagnose the missing makefile as a fatal error.

If you want make to simply ignore a makefile which does not exist and cannot be remade, with no error message, use the -include directive instead of include, like this:

     -include FILENAMES...

This is acts like include in every way except that there is no error (not even a warning) if any of the FILENAMES do not exist.

The Variable MAKEFILES
======================

If the environment variable MAKEFILES is defined, make considers its value as a list of names (separated by whitespace) of additional makefiles to be read before the others.  This works much like the include directive: various directories are searched for those files (see Including Other Makefiles).  In addition, the default goal is never taken from one of these makefiles and it is not an error if the files listed in MAKEFILES are not found.

The main use of MAKEFILES is in communication between recursive invocations of make (see Recursive Use of make).  It usually is not desirable to set the environment variable before a top-level invocation of make, because it is usually better not to mess with a makefile from outside.  However, if you are running make without a specific makefile, a makefile in MAKEFILES can do useful things to help the built-in implicit rules work better, such as defining search paths (see Directory Search).

Some users are tempted to set MAKEFILES in the environment automatically on login, and program makefiles to expect this to be done. This is a very bad idea, because such makefiles will fail to work if run by anyone else.  It is much better to write explicit include directives in the makefiles.  See Including Other Makefiles.

How Makefiles Are Remade
========================

Sometimes makefiles can be remade from other files, such as RCS or SCCS files.  If a makefile can be remade from other files, you probably want make to get an up-to-date version of the makefile to read in.

To this end, after reading in all makefiles, make will consider each as a goal target and attempt to update it.  If a makefile has a rule which says how to update it (found either in that very makefile or in another one) or if an implicit rule applies to it (see Using Implicit Rules), it will be updated if necessary.  After all makefiles have been checked, if any have actually been changed, make starts with a clean slate and reads all the makefiles over again.  (It will also attempt to update each of them over again, but normally this will not change them again, since they are already up to date.)

If the makefiles specify a double-colon rule to remake a file with commands but no dependencies, that file will always be remade (see Double-Colon).  In the case of makefiles, a makefile that has a double-colon rule with commands but no dependencies will be remade every time make is run, and then again after make starts over and reads the makefiles in again.  This would cause an infinite loop: make would constantly remake the makefile, and never do anything else.  So, to avoid this, make will not attempt to remake makefiles which are specified as double-colon targets but have no dependencies.

If you do not specify any makefiles to be read with -f or --file options, make will try the default makefile names; see What Name to Give Your Makefile.  Unlike makefiles explicitly requested with -f or --file options, make is not certain that these makefiles should exist.  However, if a default makefile does not exist but can be created by running make rules, you probably want the rules to be run so that the makefile can be used.

Therefore, if none of the default makefiles exists, make will try to make each of them in the same order in which they are searched for (see What Name to Give Your Makefile) until it succeeds in making one, or it runs out of names to try.  Note that it is not an error if make cannot find or make any makefile; a makefile is not always necessary.

When you use the -t or --touch option (see Instead of Executing the Commands), you would not want to use an out-of-date makefile to decide which targets to touch.  So the -t option has no effect on updating makefiles; they are really updated even if -t is specified. Likewise, -q (or --question) and -n (or --just-print) do not prevent updating of makefiles, because an out-of-date makefile would result in the wrong output for other targets. Thus, make -f mfile -n foo will update mfile, read it in, and then print the commands to update foo and its dependencies without running them.  The commands printed for foo will be those specified in the updated contents of mfile.

However, on occasion you might actually wish to prevent updating of even the makefiles.  You can do this by specifying the makefiles as goals in the command line as well as specifying them as makefiles.  When the makefile name is specified explicitly as a goal, the options -t and so on do apply to them.

Thus, make -f mfile -n mfile foo would read the makefile mfile, print the commands needed to update it without actually running them, and then print the commands needed to update foo without running them.  The commands for foo will be those specified by the existing contents of mfile.

Overriding Part of Another Makefile
===================================

Sometimes it is useful to have a makefile that is mostly just like another makefile.  You can often use the include directive to include one in the other, and add more targets or variable definitions. However, if the two makefiles give different commands for the same target, make will not let you just do this.  But there is another way.

In the containing makefile (the one that wants to include the other), you can use a match-anything pattern rule to say that to remake any target that cannot be made from the information in the containing makefile, make should look in another makefile. See Pattern Rules, for more information on pattern rules.

For example, if you have a makefile called Makefile that says how to make the target foo (and other targets), you can write a makefile called GNUmakefile that contains:

     foo:
             frobnicate > foo

     %: force
             @$(MAKE) -f Makefile $@
     force: ;

If you say make foo, make will find GNUmakefile, read it, and see that to make foo, it needs to run the command frobnicate > foo.  If you say make bar, make will find no way to make bar in GNUmakefile, so it will use the commands from the pattern rule: make -f Makefile bar.  If Makefile provides a rule for updating bar, make will apply the rule.  And likewise for any other target that GNUmakefile does not say how to make.

The way this works is that the pattern rule has a pattern of just %, so it matches any target whatever.  The rule specifies a dependency force, to guarantee that the commands will be run even if the target file already exists.  We give force target empty commands to prevent make from searching for an implicit rule to build it---otherwise it would apply the same match-anything rule to force itself and create a dependency loop!

Writing Rules
*************

A rule appears in the makefile and says when and how to remake certain files, called the rule's targets (most often only one per rule). It lists the other files that are the dependencies of the target, and commands to use to create or update the target.

The order of rules is not significant, except for determining the default goal: the target for make to consider, if you do not otherwise specify one.  The default goal is the target of the first rule in the first makefile.  If the first rule has multiple targets, only the first target is taken as the default.  There are two exceptions: a target starting with a period is not a default unless it contains one or more slashes, /, as well; and, a target that defines a pattern rule has no effect on the default goal. (see Defining and Redefining Pattern Rules.)

Therefore, we usually write the makefile so that the first rule is the one for compiling the entire program or all the programs described by the makefile (often with a target called all). See Arguments to Specify the Goals.

Rule Example
============

Here is an example of a rule:

     foo.o : foo.c defs.h       # module for twiddling the frobs
             cc -c -g foo.c

Its target is foo.o and its dependencies are foo.c and defs.h.  It has one command, which is cc -c -g foo.c. The command line starts with a tab to identify it as a command.

This rule says two things:

  * How to decide whether foo.o is out of date: it is out of date if it does not exist, or if either foo.c or defs.h is more recent than it.

  * How to update the file foo.o: by running cc as stated. The command does not explicitly mention defs.h, but we presume that foo.c includes it, and that that is why defs.h was added to the dependencies.

Rule Syntax
===========

In general, a rule looks like this:

     TARGETS : DEPENDENCIES
             COMMAND
             ...

or like this:

     TARGETS : DEPENDENCIES ; COMMAND
             COMMAND
             ...

The TARGETS are file names, separated by spaces.  Wildcard characters may be used (see Using Wildcard Characters in File Names) and a name of the form A(M) represents member M in archive file A (see Archive Members as Targets). Usually there is only one target per rule, but occasionally there is a reason to have more (see Multiple Targets in a Rule).

The COMMAND lines start with a tab character.  The first command may appear on the line after the dependencies, with a tab character, or may appear on the same line, with a semicolon.  Either way, the effect is the same.  See Writing the Commands in Rules.

Because dollar signs are used to start variable references, if you really want a dollar sign in a rule you must write two of them, $$ (see How to Use Variables). You may split a long line by inserting a backslash followed by a newline, but this is not required, as make places no limit on the length of a line in a makefile.

A rule tells make two things: when the targets are out of date, and how to update them when necessary.

The criterion for being out of date is specified in terms of the DEPENDENCIES, which consist of file names separated by spaces. (Wildcards and archive members (see Archives) are allowed here too.) A target is out of date if it does not exist or if it is older than any of the dependencies (by comparison of last-modification times).  The idea is that the contents of the target file are computed based on information in the dependencies, so if any of the dependencies changes, the contents of the existing target file are no longer necessarily valid.

How to update is specified by COMMANDS.  These are lines to be executed by the shell (normally sh), but with some extra features (see Writing the Commands in Rules).

Using Wildcard Characters in File Names
=======================================

A single file name can specify many files using wildcard characters. The wildcard characters in make are *, ? and [...], the same as in the Bourne shell.  For example, *.c specifies a list of all the files (in the working directory) whose names end in .c.

The character ~ at the beginning of a file name also has special significance.  If alone, or followed by a slash, it represents your home directory.  For example ~/bin expands to /home/you/bin. If the ~ is followed by a word, the string represents the home directory of the user named by that word.  For example ~john/bin expands to /home/john/bin.

Wildcard expansion happens automatically in targets, in dependencies, and in commands (where the shell does the expansion).  In other contexts, wildcard expansion happens only if you request it explicitly with the wildcard function.

The special significance of a wildcard character can be turned off by preceding it with a backslash.  Thus, foo\*bar would refer to a specific file whose name consists of foo, an asterisk, and bar.

Wildcard Examples
-----------------

Wildcards can be used in the commands of a rule, where they are expanded by the shell.  For example, here is a rule to delete all the object files:

     clean:
             rm -f *.o

Wildcards are also useful in the dependencies of a rule.  With the following rule in the makefile, make print will print all the .c files that have changed since the last time you printed them:

     print: *.c
             lpr -p $?
             touch print

This rule uses print as an empty target file; see Empty Target Files to Record Events.  (The automatic variable $? is used to print only those files that have changed; see Automatic Variables.)

Wildcard expansion does not happen when you define a variable.  Thus, if you write this:

     objects = *.o

then the value of the variable objects is the actual string *.o.  However, if you use the value of objects in a target, dependency or command, wildcard expansion will take place at that time. To set objects to the expansion, instead use:

     objects := $(wildcard *.o)

See Wildcard Function.

Pitfalls of Using Wildcards
---------------------------

Now here is an example of a naive way of using wildcard expansion, that does not do what you would intend.  Suppose you would like to say that the executable file foo is made from all the object files in the directory, and you write this:

     objects = *.o

     foo : $(objects)
             cc -o foo $(CFLAGS) $(objects)

The value of objects is the actual string *.o.  Wildcard expansion happens in the rule for foo, so that each existing .o file becomes a dependency of foo and will be recompiled if necessary.

But what if you delete all the .o files?  When a wildcard matches no files, it is left as it is, so then foo will depend on the oddly-named file *.o.  Since no such file is likely to exist, make will give you an error saying it cannot figure out how to make *.o.  This is not what you want!

Actually it is possible to obtain the desired result with wildcard expansion, but you need more sophisticated techniques, including the wildcard function and string substitution. See The Function wildcard.

The Function wildcard
---------------------

Wildcard expansion happens automatically in rules.  But wildcard expansion does not normally take place when a variable is set, or inside the arguments of a function.  If you want to do wildcard expansion in such places, you need to use the wildcard function, like this:

     $(wildcard PATTERN...)

This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match one of the given file name patterns.  If no existing file name matches a pattern, then that pattern is omitted from the output of the wildcard function.  Note that this is different from how unmatched wildcards behave in rules, where they are used verbatim rather than ignored (see Wildcard Pitfall).

One use of the wildcard function is to get a list of all the C source files in a directory, like this:

     $(wildcard *.c)

We can change the list of C source files into a list of object files by replacing the .o suffix with .c in the result, like this:

     $(patsubst %.c,%.o,$(wildcard *.c))

(Here we have used another function, patsubst. See Functions for String Substitution and Analysis.)

Thus, a makefile to compile all C source files in the directory and then link them together could be written as follows:

     objects := $(patsubst %.c,%.o,$(wildcard *.c))

     foo : $(objects)
             cc -o foo $(objects)

(This takes advantage of the implicit rule for compiling C programs, so there is no need to write explicit rules for compiling the files. See The Two Flavors of Variables, for an explanation of :=, which is a variant of =.)

Searching Directories for Dependencies
======================================

For large systems, it is often desirable to put sources in a separate directory from the binaries.  The directory search features of make facilitate this by searching several directories automatically to find a dependency.  When you redistribute the files among directories, you do not need to change the individual rules, just the search paths.

VPATH: Search Path for All Dependencies
---------------------------------------

The value of the make variable VPATH specifies a list of directories that make should search.  Most often, the directories are expected to contain dependency files that are not in the current directory; however, VPATH specifies a search list that make applies for all files, including files which are targets of rules.

Thus, if a file that is listed as a target or dependency does not exist in the current directory, make searches the directories listed in VPATH for a file with that name.  If a file is found in one of them, that file becomes the dependency.  Rules may then specify the names of source files in the dependencies as if they all existed in the current directory.  See Writing Shell Commands with Directory Search.

In the VPATH variable, directory names are separated by colons or blanks.  The order in which directories are listed is the order followed by make in its search.

For example,

     VPATH = src:../headers

specifies a path containing two directories, src and ../headers, which make searches in that order.

With this value of VPATH, the following rule,

     foo.o : foo.c

is interpreted as if it were written like this:

     foo.o : src/foo.c

assuming the file foo.c does not exist in the current directory but is found in the directory src.

The vpath Directive
-------------------

Similar to the VPATH variable but more selective is the vpath directive (note lower case), which allows you to specify a search path for a particular class of file names, those that match a particular pattern.  Thus you can supply certain search directories for one class of file names and other directories (or none) for other file names.

There are three forms of the vpath directive:

vpath PATTERN DIRECTORIES
     Specify the search path DIRECTORIES for file names that match PATTERN.

     The search path, DIRECTORIES, is a list of directories to be searched, separated by colons or blanks, just like the search path used in the VPATH variable.

vpath PATTERN
     Clear out the search path associated with PATTERN.

vpath

     Clear all search paths previously specified with vpath directives.

A vpath pattern is a string containing a % character.  The string must match the file name of a dependency that is being searched for, the % character matching any sequence of zero or more characters (as in pattern rules; see Defining and Redefining Pattern Rules).  For example, %.h matches files that end in .h.  (If there is no %, the pattern must match the dependency exactly, which is not useful very often.)

% characters in a vpath directive's pattern can be quoted with preceding backslashes (\).  Backslashes that would otherwise quote % characters can be quoted with more backslashes. Backslashes that quote % characters or other backslashes are removed from the pattern before it is compared to file names.  Backslashes that are not in danger of quoting % characters go unmolested.

When a dependency fails to exist in the current directory, if the PATTERN in a vpath directive matches the name of the dependency file, then the DIRECTORIES in that directive are searched just like (and before) the directories in the VPATH variable.

For example,

     vpath %.h ../headers

tells make to look for any dependency whose name ends in .h in the directory ../headers if the file is not found in the current directory.

If several vpath patterns match the dependency file's name, then make processes each matching vpath directive one by one, searching all the directories mentioned in each directive.  make handles multiple vpath directives in the order in which they appear in the makefile; multiple directives with the same pattern are independent of each other.

Thus,

     vpath %.c foo
     vpath %   blish
     vpath %.c bar

will look for a file ending in .c in foo, then blish, then bar, while

     vpath %.c foo:bar
     vpath %   blish

will look for a file ending in .c in foo, then bar, then blish.

Writing Shell Commands with Directory Search
--------------------------------------------

When a dependency is found in another directory through directory search, this cannot change the commands of the rule; they will execute as written. Therefore, you must write the commands with care so that they will look for the dependency in the directory where make finds it.

This is done with the automatic variables such as $^ (see Automatic Variables). For instance, the value of $^ is a list of all the dependencies of the rule, including the names of the directories in which they were found, and the value of $@ is the target.  Thus:

     foo.o : foo.c
             cc -c $(CFLAGS) $^ -o $@

(The variable CFLAGS exists so you can specify flags for C compilation by implicit rules; we use it here for consistency so it will affect all C compilations uniformly; see Variables Used by Implicit Rules.)

Often the dependencies include header files as well, which you do not want to mention in the commands.  The automatic variable $< is just the first dependency:

     VPATH = src:../headers
     foo.o : foo.c defs.h hack.h
             cc -c $(CFLAGS) $< -o $@

Directory Search and Implicit Rules
-----------------------------------

The search through the directories specified in VPATH or with vpath also happens during consideration of implicit rules (see Using Implicit Rules).

For example, when a file foo.o has no explicit rule, make considers implicit rules, such as the built-in rule to compile foo.c if that file exists.  If such a file is lacking in the current directory, the appropriate directories are searched for it.  If foo.c exists (or is mentioned in the makefile) in any of the directories, the implicit rule for C compilation is applied.

The commands of implicit rules normally use automatic variables as a matter of necessity; consequently they will use the file names found by directory search with no extra effort.

Directory Search for Link Libraries
-----------------------------------

Directory search applies in a special way to libraries used with the linker.  This special feature comes into play when you write a dependency whose name is of the form -lNAME.  (You can tell something strange is going on here because the dependency is normally the name of a file, and the file name of the library looks like libNAME.a, not like -lNAME.)

When a dependency's name has the form -lNAME, make handles it specially by searching for the file libNAME.a in the current directory, in directories specified by matching vpath search paths and the VPATH search path, and then in the directories /lib, /usr/lib, and PREFIX/lib (normally /usr/local/lib).

For example,

     foo : foo.c -lcurses
             cc $^ -o $@

would cause the command cc foo.c /usr/lib/libcurses.a -o foo to be executed when foo is older than foo.c or than /usr/lib/libcurses.a.

Phony Targets
=============

A phony target is one that is not really the name of a file.  It is just a name for some commands to be executed when you make an explicit request. There are two reasons to use a phony target: to avoid a conflict with a file of the same name, and to improve performance.

If you write a rule whose commands will not create the target file, the commands will be executed every time the target comes up for remaking. Here is an example:

     clean:
             rm *.o temp

Because the rm command does not create a file named clean, probably no such file will ever exist.  Therefore, the rm command will be executed every time you say make clean.

The phony target will cease to work if anything ever does create a file named clean in this directory.  Since it has no dependencies, the file clean would inevitably be considered up to date, and its commands would not be executed.  To avoid this problem, you can explicitly declare the target to be phony, using the special target .PHONY (see Special Built-in Target Names) as follows:

     .PHONY : clean

Once this is done, make clean will run the commands regardless of whether there is a file named clean.

Since it knows that phony targets do not name actual files that could be remade from other files, make skips the implicit rule search for phony targets (see Implicit Rules).  This is why declaring a target phony is good for performance, even if you are not worried about the actual file existing.

Thus, you first write the line that states that clean is a phony target, then you write the rule, like this:

     .PHONY: clean
     clean:
             rm *.o temp

A phony target should not be a dependency of a real target file; if it is, its commands are run every time make goes to update that file.  As long as a phony target is never a dependency of a real target, the phony target commands will be executed only when the phony target is a specified goal (see Arguments to Specify the Goals).

Phony targets can have dependencies.  When one directory contains multiple programs, it is most convenient to describe all of the programs in one makefile ./Makefile.  Since the target remade by default will be the first one in the makefile, it is common to make this a phony target named all and give it, as dependencies, all the individual programs.  For example:

     all : prog1 prog2 prog3
     .PHONY : all

     prog1 : prog1.o utils.o
             cc -o prog1 prog1.o utils.o

     prog2 : prog2.o
             cc -o prog2 prog2.o

     prog3 : prog3.o sort.o utils.o
             cc -o prog3 prog3.o sort.o utils.o

Now you can say just make to remake all three programs, or specify as arguments the ones to remake (as in make prog1 prog3).

When one phony target is a dependency of another, it serves as a subroutine of the other.  For example, here make cleanall will delete the object files, the difference files, and the file program:

     .PHONY: cleanall cleanobj cleandiff

     cleanall : cleanobj cleandiff
             rm program

     cleanobj :
             rm *.o

     cleandiff :
             rm *.diff

Rules without Commands or Dependencies
======================================

If a rule has no dependencies or commands, and the target of the rule is a nonexistent file, then make imagines this target to have been updated whenever its rule is run.  This implies that all targets depending on this one will always have their commands run.

An example will illustrate this:

     clean: FORCE
             rm $(objects)
     FORCE:

Here the target FORCE satisfies the special conditions, so the target clean that depends on it is forced to run its commands. There is nothing special about the name FORCE, but that is one name commonly used this way.

As you can see, using FORCE this way has the same results as using .PHONY: clean.

Using .PHONY is more explicit and more efficient.  However, other versions of make do not support .PHONY; thus FORCE appears in many makefiles.  See Phony Targets.

Empty Target Files to Record Events
===================================

The empty target is a variant of the phony target; it is used to hold commands for an action that you request explicitly from time to time. Unlike a phony target, this target file can really exist; but the file's contents do not matter, and usually are empty.

The purpose of the empty target file is to record, with its last-modification time, when the rule's commands were last executed.  It does so because one of the commands is a touch command to update the target file.

The empty target file must have some dependencies.  When you ask to remake the empty target, the commands are executed if any dependency is more recent than the target; in other words, if a dependency has changed since the last time you remade the target.  Here is an example:

     print: foo.c bar.c
             lpr -p $?
             touch print

With this rule, make print will execute the lpr command if either source file has changed since the last make print.  The automatic variable $? is used to print only those files that have changed (see Automatic Variables).

Special Built-in Target Names
=============================

Certain names have special meanings if they appear as targets.

.PHONY

     The dependencies of the special target .PHONY are considered to be phony targets.  When it is time to consider such a target, make will run its commands unconditionally, regardless of whether a file with that name exists or what its last-modification time is.  See Phony Targets.

.SUFFIXES

     The dependencies of the special target .SUFFIXES are the list of suffixes to be used in checking for suffix rules. See Old-Fashioned Suffix Rules.

.DEFAULT

     The commands specified for .DEFAULT are used for any target for which no rules are found (either explicit rules or implicit rules). See Last Resort.  If .DEFAULT commands are specified, every file mentioned as a dependency, but not as a target in a rule, will have these commands executed on its behalf.  See Implicit Rule Search Algorithm.

.PRECIOUS

     The targets which .PRECIOUS depends on are given the following special treatment: if make is killed or interrupted during the execution of their commands, the target is not deleted. See Interrupting or Killing make. Also, if the target is an intermediate file, it will not be deleted after it is no longer needed, as is normally done. See Chains of Implicit Rules.

     You can also list the target pattern of an implicit rule (such as %.o) as a dependency file of the special target .PRECIOUS to preserve intermediate files created by rules whose target patterns match that file's name.

.IGNORE

     If you specify dependencies for .IGNORE, then make will ignore errors in execution of the commands run for those particular files.  The commands for .IGNORE are not meaningful.

     If mentioned as a target with no dependencies, .IGNORE says to ignore errors in execution of commands for all files.  This usage of .IGNORE is supported only for historical compatibility.  Since this affects every command in the makefile, it is not very useful; we recommend you use the more selective ways to ignore errors in specific commands.  See Errors in Commands.

.SILENT

     If you specify dependencies for .SILENT, then make will not the print commands to remake those particular files before executing them.  The commands for .SILENT are not meaningful.

     If mentioned as a target with no dependencies, .SILENT says not to print any commands before executing them.  This usage of .SILENT is supported only for historical compatibility.  We recommend you use the more selective ways to silence specific commands. See Command Echoing.  If you want to silence all commands for a particular run of make, use the -s or --silent option (see Options Summary).

.EXPORT_ALL_VARIABLES

     Simply by being mentioned as a target, this tells make to export all variables to child processes by default. See Communicating Variables to a Sub-make.

Any defined implicit rule suffix also counts as a special target if it appears as a target, and so does the concatenation of two suffixes, such as .c.o.  These targets are suffix rules, an obsolete way of defining implicit rules (but a way still widely used).  In principle, any target name could be special in this way if you break it in two and add both pieces to the suffix list.  In practice, suffixes normally begin with ., so these special target names also begin with .. See Old-Fashioned Suffix Rules.

Multiple Targets in a Rule
==========================

A rule with multiple targets is equivalent to writing many rules, each with one target, and all identical aside from that.  The same commands apply to all the targets, but their effects may vary because you can substitute the actual target name into the command using $@.  The rule contributes the same dependencies to all the targets also.

This is useful in two cases.

  * You want just dependencies, no commands.  For example:

          kbd.o command.o files.o: command.h

     gives an additional dependency to each of the three object files mentioned.

  * Similar commands work for all the targets.  The commands do not need to be absolutely identical, since the automatic variable $@ can be used to substitute the particular target to be remade into the commands (see Automatic Variables).  For example:

          bigoutput littleoutput : text.g
                  generate text.g -$(subst output,,$@) > $@

     is equivalent to

          bigoutput : text.g
                  generate text.g -big > bigoutput
          littleoutput : text.g
                  generate text.g -little > littleoutput

     Here we assume the hypothetical program generate makes two types of output, one if given -big and one if given -little. See Functions for String Substitution and Analysis, for an explanation of the subst function.

Suppose you would like to vary the dependencies according to the target, much as the variable $@ allows you to vary the commands. You cannot do this with multiple targets in an ordinary rule, but you can do it with a static pattern rule. See Static Pattern Rules.

Multiple Rules for One Target
=============================

One file can be the target of several rules.  All the dependencies mentioned in all the rules are merged into one list of dependencies for the target.  If the target is older than any dependency from any rule, the commands are executed.

There can only be one set of commands to be executed for a file. If more than one rule gives commands for the same file, make uses the last set given and prints an error message. (As a special case, if the file's name begins with a dot, no error message is printed.  This odd behavior is only for compatibility with other implementations of make.) There is no reason to write your makefiles this way; that is why make gives you an error message.

An extra rule with just dependencies can be used to give a few extra dependencies to many files at once.  For example, one usually has a variable named objects containing a list of all the compiler output files in the system being made.  An easy way to say that all of them must be recompiled if config.h changes is to write the following:

     objects = foo.o bar.o
     foo.o : defs.h
     bar.o : defs.h test.h
     $(objects) : config.h

This could be inserted or taken out without changing the rules that really specify how to make the object files, making it a convenient form to use if you wish to add the additional dependency intermittently.

Another wrinkle is that the additional dependencies could be specified with a variable that you set with a command argument to make (see Overriding Variables).  For example,

     extradeps=
     $(objects) : $(extradeps)

means that the command make extradeps=foo.h will consider foo.h as a dependency of each object file, but plain make will not.

If none of the explicit rules for a target has commands, then make searches for an applicable implicit rule to find some commands see Using Implicit Rules).

Static Pattern Rules
====================

Static pattern rules are rules which specify multiple targets and construct the dependency names for each target based on the target name. They are more general than ordinary rules with multiple targets because the targets do not have to have identical dependencies.  Their dependencies must be analogous, but not necessarily identical.

Syntax of Static Pattern Rules
------------------------------

Here is the syntax of a static pattern rule:

     TARGETS ...: TARGET-PATTERN: DEP-PATTERNS ...
             COMMANDS
             ...

The TARGETS list specifies the targets that the rule applies to. The targets can contain wildcard characters, just like the targets of ordinary rules (see Using Wildcard Characters in File Names).

The TARGET-PATTERN and DEP-PATTERNS say how to compute the dependencies of each target.  Each target is matched against the TARGET-PATTERN to extract a part of the target name, called the stem.  This stem is substituted into each of the DEP-PATTERNS to make the dependency names (one from each DEP-PATTERN).

Each pattern normally contains the character % just once.  When the TARGET-PATTERN matches a target, the % can match any part of the target name; this part is called the stem.  The rest of the pattern must match exactly.  For example, the target foo.o matches the pattern %.o, with foo as the stem.  The targets foo.c and foo.out do not match that pattern.

The dependency names for each target are made by substituting the stem for the % in each dependency pattern.  For example, if one dependency pattern is %.c, then substitution of the stem foo gives the dependency name foo.c.  It is legitimate to write a dependency pattern that does not contain %; then this dependency is the same for all targets.

% characters in pattern rules can be quoted with preceding backslashes (\).  Backslashes that would otherwise quote % characters can be quoted with more backslashes.  Backslashes that quote % characters or other backslashes are removed from the pattern before it is compared to file names or has a stem substituted into it. Backslashes that are not in danger of quoting % characters go unmolested.  For example, the pattern the\%weird\\%pattern\\ has the%weird\ preceding the operative % character, and pattern\\ following it.  The final two backslashes are left alone because they cannot affect any % character.

Here is an example, which compiles each of foo.o and bar.o from the corresponding .c file:

     objects = foo.o bar.o

     $(objects): %.o: %.c
             $(CC) -c $(CFLAGS) $< -o $@

Here $< is the automatic variable that holds the name of the dependency and $@ is the automatic variable that holds the name of the target; see Automatic Variables.

Each target specified must match the target pattern; a warning is issued for each target that does not.  If you have a list of files, only some of which will match the pattern, you can use the filter function to remove nonmatching file names (see Functions for String Substitution and Analysis):

     files = foo.elc bar.o lose.o

     $(filter %.o,$(files)): %.o: %.c
             $(CC) -c $(CFLAGS) $< -o $@
     $(filter %.elc,$(files)): %.elc: %.el
             emacs -f batch-byte-compile $<

In this example the result of $(filter %.o,$(files)) is bar.o lose.o, and the first static pattern rule causes each of these object files to be updated by compiling the corresponding C source file.  The result of $(filter %.elc,$(files)) is foo.elc, so that file is made from foo.el.

Another example shows how to use $* in static pattern rules:

     bigoutput littleoutput : %output : text.g
             generate text.g -$* > $@

When the generate command is run, $* will expand to the stem, either big or little.

Static Pattern Rules versus Implicit Rules
------------------------------------------

A static pattern rule has much in common with an implicit rule defined as a pattern rule (see Defining and Redefining Pattern Rules). Both have a pattern for the target and patterns for constructing the names of dependencies.  The difference is in how make decides when the rule applies.

An implicit rule can apply to any target that matches its pattern, but it does apply only when the target has no commands otherwise specified, and only when the dependencies can be found.  If more than one implicit rule appears applicable, only one applies; the choice depends on the order of rules.

By contrast, a static pattern rule applies to the precise list of targets that you specify in the rule.  It cannot apply to any other target and it invariably does apply to each of the targets specified.  If two conflicting rules apply, and both have commands, that's an error.

The static pattern rule can be better than an implicit rule for these reasons:

  * You may wish to override the usual implicit rule for a few files whose names cannot be categorized syntactically but can be given in an explicit list.

  * If you cannot be sure of the precise contents of the directories you are using, you may not be sure which other irrelevant files might lead make to use the wrong implicit rule.  The choice might depend on the order in which the implicit rule search is done. With static pattern rules, there is no uncertainty: each rule applies to precisely the targets specified.

Double-Colon Rules
==================

Double-colon rules are rules written with :: instead of : after the target names.  They are handled differently from ordinary rules when the same target appears in more than one rule.

When a target appears in multiple rules, all the rules must be the same type: all ordinary, or all double-colon.  If they are double-colon, each of them is independent of the others.  Each double-colon rule's commands are executed if the target is older than any dependencies of that rule.  This can result in executing none, any, or all of the double-colon rules.

Double-colon rules with the same target are in fact completely separate from one another.  Each double-colon rule is processed individually, just as rules with different targets are processed.

The double-colon rules for a target are executed in the order they appear in the makefile.  However, the cases where double-colon rules really make sense are those where the order of executing the commands would not matter.

Double-colon rules are somewhat obscure and not often very useful; they provide a mechanism for cases in which the method used to update a target differs depending on which dependency files caused the update, and such cases are rare.

Each double-colon rule should specify commands; if it does not, an implicit rule will be used if one applies. See Using Implicit Rules.

Generating Dependencies Automatically
=====================================

In the makefile for a program, many of the rules you need to write often say only that some object file depends on some header file.  For example, if main.c uses defs.h via an #include, you would write:

     main.o: defs.h

You need this rule so that make knows that it must remake main.o whenever defs.h changes.  You can see that for a large program you would have to write dozens of such rules in your makefile.  And, you must always be very careful to update the makefile every time you add or remove an #include.

To avoid this hassle, most modern C compilers can write these rules for you, by looking at the #include lines in the source files. Usually this is done with the -M option to the compiler. For example, the command:

     cc -M main.c

generates the output:

     main.o : main.c defs.h

Thus you no longer have to write all those rules yourself. The compiler will do it for you.

Note that such a dependency constitutes mentioning main.o in a makefile, so it can never be considered an intermediate file by implicit rule search.  This means that make won't ever remove the file after using it; see Chains of Implicit Rules.

With old make programs, it was traditional practice to use this compiler feature to generate dependencies on demand with a command like make depend.  That command would create a file depend containing all the automatically-generated dependencies; then the makefile could use include to read them in (see Include).

In GNU make, the feature of remaking makefiles makes this practice obsolete---you need never tell make explicitly to regenerate the dependencies, because it always regenerates any makefile that is out of date.  See Remaking Makefiles.

The practice we recommend for automatic dependency generation is to have one makefile corresponding to each source file.  For each source file NAME.c there is a makefile NAME.d which lists what files the object file NAME.o depends on.  That way only the source files that have changed need to be rescanned to produce the new dependencies.

Here is the pattern rule to generate a file of dependencies (i.e., a makefile) called NAME.d from a C source file called NAME.c:

     %.d: %.c
             $(SHELL) -ec '$(CC) -M $(CPPFLAGS) $< \
                           | sed '\''s/$*\\.o[ :]*/& $@/g'\'' > $@'

See Pattern Rules, for information on defining pattern rules.  The -e flag to the shell makes it exit immediately if the $(CC) command fails (exits with a nonzero status).  Normally the shell exits with the status of the last command in the pipeline (sed in this case), so make would not notice a nonzero status from the compiler.

With the GNU C compiler, you may wish to use the -MM flag instead of -M.  This omits dependencies on system header files. See Options Controlling the Preprocessor (Using GNU CC), for details.

The purpose of the sed command is to translate (for example):

     main.o : main.c defs.h

into:

     main.o main.d : main.c defs.h

This makes each .d file depend on all the source and header files that the corresponding .o file depends on.  make then knows it must regenerate the dependencies whenever any of the source or header files changes.

Once you've defined the rule to remake the .d files, you then use the include directive to read them all in. See Include.  For example:

     sources = foo.c bar.c

     include $(sources:.c=.d)

(This example uses a substitution variable reference to translate the list of source files foo.c bar.c into a list of dependency makefiles, foo.d bar.d.  See Substitution Refs, for full information on substitution references.)  Since the .d files are makefiles like any others, make will remake them as necessary with no further work from you.  See Remaking Makefiles.

Writing the Commands in Rules
*****************************

The commands of a rule consist of shell command lines to be executed one by one.  Each command line must start with a tab, except that the first command line may be attached to the target-and-dependencies line with a semicolon in between.  Blank lines and lines of just comments may appear among the command lines; they are ignored.  (But beware, an apparently ``blank'' line that begins with a tab is not blank!  It is an empty command; see Empty Commands.)

Users use many different shell programs, but commands in makefiles are always interpreted by /bin/sh unless the makefile specifies otherwise.  See Command Execution.

The shell that is in use determines whether comments can be written on command lines, and what syntax they use.  When the shell is /bin/sh, a # starts a comment that extends to the end of the line.  The # does not have to be at the beginning of a line. Text on a line before a # is not part of the comment.

Command Echoing
===============

Normally make prints each command line before it is executed. We call this echoing because it gives the appearance that you are typing the commands yourself.

When a line starts with @, the echoing of that line is suppressed. The @ is discarded before the command is passed to the shell. Typically you would use this for a command whose only effect is to print something, such as an echo command to indicate progress through the makefile:

     @echo About to make distribution files

When make is given the flag -n or --just-print, echoing is all that happens, no execution.  See Summary of Options.  In this case and only this case, even the commands starting with @ are printed.  This flag is useful for finding out which commands make thinks are necessary without actually doing them.

The -s or --silent flag to make prevents all echoing, as if all commands started with @.  A rule in the makefile for the special target .SILENT without dependencies has the same effect (see Special Built-in Target Names). .SILENT is essentially obsolete since @ is more flexible.

Command Execution
=================

When it is time to execute commands to update a target, they are executed by making a new subshell for each line.  (In practice, make may take shortcuts that do not affect the results.)

Please note: this implies that shell commands such as cd that set variables local to each process will not affect the following command lines.  If you want to use cd to affect the next command, put the two on a single line with a semicolon between them.  Then make will consider them a single command and pass them, together, to a shell which will execute them in sequence.  For example:

     foo : bar/lose
             cd bar; gobble lose > ../foo

If you would like to split a single shell command into multiple lines of text, you must use a backslash at the end of all but the last subline. Such a sequence of lines is combined into a single line, by deleting the backslash-newline sequences, before passing it to the shell.  Thus, the following is equivalent to the preceding example:

     foo : bar/lose
             cd bar;  \
             gobble lose > ../foo

The program used as the shell is taken from the variable SHELL. By default, the program /bin/sh is used.

Unlike most variables, the variable SHELL is never set from the environment.  This is because the SHELL environment variable is used to specify your personal choice of shell program for interactive use.  It would be very bad for personal choices like this to affect the functioning of makefiles.  See Variables from the Environment.

Parallel Execution
==================

GNU make knows how to execute several commands at once. Normally, make will execute only one command at a time, waiting for it to finish before executing the next.  However, the -j or --jobs option tells make to execute many commands simultaneously.

If the -j option is followed by an integer, this is the number of commands to execute at once; this is called the number of job slots. If there is nothing looking like an integer after the -j option, there is no limit on the number of job slots.  The default number of job slots is one, which means serial execution (one thing at a time).

One unpleasant consequence of running several commands simultaneously is that output from all of the commands comes when the commands send it, so messages from different commands may be interspersed.

Another problem is that two processes cannot both take input from the same device; so to make sure that only one command tries to take input from the terminal at once, make will invalidate the standard input streams of all but one running command.  This means that attempting to read from standard input will usually be a fatal error (a Broken pipe signal) for most child processes if there are several.

It is unpredictable which command will have a valid standard input stream (which will come from the terminal, or wherever you redirect the standard input of make).  The first command run will always get it first, and the first command started after that one finishes will get it next, and so on.

We will change how this aspect of make works if we find a better alternative.  In the mean time, you should not rely on any command using standard input at all if you are using the parallel execution feature; but if you are not using this feature, then standard input works normally in all commands.

If a command fails (is killed by a signal or exits with a nonzero status), and errors are not ignored for that command (see Errors in Commands), the remaining command lines to remake the same target will not be run. If a command fails and the -k or --keep-going option was not given (see Summary of Options), make aborts execution.  If make terminates for any reason (including a signal) with child processes running, it waits for them to finish before actually exiting.

When the system is heavily loaded, you will probably want to run fewer jobs than when it is lightly loaded.  You can use the -l option to tell make to limit the number of jobs to run at once, based on the load average.  The -l or --max-load option is followed by a floating-point number.  For example,

     -l 2.5

will not let make start more than one job if the load average is above 2.5.  The -l option with no following number removes the load limit, if one was given with a previous -l option.

More precisely, when make goes to start up a job, and it already has at least one job running, it checks the current load average; if it is not lower than the limit given with -l, make waits until the load average goes below that limit, or until all the other jobs finish.

By default, there is no load limit.

Errors in Commands
==================

After each shell command returns, make looks at its exit status. If the command completed successfully, the next command line is executed in a new shell; after the last command line is finished, the rule is finished.

If there is an error (the exit status is nonzero), make gives up on the current rule, and perhaps on all rules.

Sometimes the failure of a certain command does not indicate a problem. For example, you may use the mkdir command to ensure that a directory exists.  If the directory already exists, mkdir will report an error, but you probably want make to continue regardless.

To ignore errors in a command line, write a - at the beginning of the line's text (after the initial tab).  The - is discarded before the command is passed to the shell for execution.

For example,

     clean:
             -rm -f *.o

This causes rm to continue even if it is unable to remove a file.

When you run make with the -i or --ignore-errors flag, errors are ignored in all commands of all rules.  A rule in the makefile for the special target .IGNORE has the same effect, if there are no dependencies.  These ways of ignoring errors are obsolete because - is more flexible.

When errors are to be ignored, because of either a - or the -i flag, make treats an error return just like success, except that it prints out a message that tells you the status code the command exited with, and says that the error has been ignored.

When an error happens that make has not been told to ignore, it implies that the current target cannot be correctly remade, and neither can any other that depends on it either directly or indirectly.  No further commands will be executed for these targets, since their preconditions have not been achieved.

Normally make gives up immediately in this circumstance, returning a nonzero status.  However, if the -k or --keep-going flag is specified, make continues to consider the other dependencies of the pending targets, remaking them if necessary, before it gives up and returns nonzero status. For example, after an error in compiling one object file, make -k will continue compiling other object files even though it already knows that linking them will be impossible.  See Summary of Options.

The usual behavior assumes that your purpose is to get the specified targets up to date; once make learns that this is impossible, it might as well report the failure immediately.  The -k option says that the real purpose is to test as many of the changes made in the program as possible, perhaps to find several independent problems so that you can correct them all before the next attempt to compile.  This is why Emacs' compile command passes the -k flag by default.

Usually when a command fails, if it has changed the target file at all, the file is corrupted and cannot be used---or at least it is not completely updated.  Yet the file's timestamp says that it is now up to date, so the next time make runs, it will not try to update that file.  The situation is just the same as when the command is killed by a signal; see Interrupts.  So generally the right thing to do is to delete the target file if the command fails after beginning to change the file.  make will do this if .DELETE_ON_ERROR appears as a target.  This is almost always what you want make to do, but it is not historical practice; so for compatibility, you must explicitly request it.

Interrupting or Killing make
============================

If make gets a fatal signal while a command is executing, it may delete the target file that the command was supposed to update.  This is done if the target file's last-modification time has changed since make first checked it.

The purpose of deleting the target is to make sure that it is remade from scratch when make is next run.  Why is this?  Suppose you type Ctrl-c while a compiler is running, and it has begun to write an object file foo.o.  The Ctrl-c kills the compiler, resulting in an incomplete file whose last-modification time is newer than the source file foo.c.  But make also receives the Ctrl-c signal and deletes this incomplete file.  If make did not do this, the next invocation of make would think that foo.o did not require updating---resulting in a strange error message from the linker when it tries to link an object file half of which is missing.

You can prevent the deletion of a target file in this way by making the special target .PRECIOUS depend on it.  Before remaking a target, make checks to see whether it appears on the dependencies of .PRECIOUS, and thereby decides whether the target should be deleted if a signal happens.  Some reasons why you might do this are that the target is updated in some atomic fashion, or exists only to record a modification-time (its contents do not matter), or must exist at all times to prevent other sorts of trouble.

Recursive Use of make
=====================

Recursive use of make means using make as a command in a makefile.  This technique is useful when you want separate makefiles for various subsystems that compose a larger system.  For example, suppose you have a subdirectory subdir which has its own makefile, and you would like the containing directory's makefile to run make on the subdirectory.  You can do it by writing this:

     subsystem:
             cd subdir; $(MAKE)

or, equivalently, this (see Summary of Options):

     subsystem:
             $(MAKE) -C subdir

You can write recursive make commands just by copying this example, but there are many things to know about how they work and why, and about how the sub-make relates to the top-level make.

How the MAKE Variable Works
---------------------------

Recursive make commands should always use the variable MAKE, not the explicit command name make, as shown here:

     subsystem:
             cd subdir; $(MAKE)

The value of this variable is the file name with which make was invoked.  If this file name was /bin/make, then the command executed is cd subdir; /bin/make.  If you use a special version of make to run the top-level makefile, the same special version will be executed for recursive invocations.

As a special feature, using the variable MAKE in the commands of a rule alters the effects of the -t (--touch), -n (--just-print), or -q (--question) option. Using the MAKE variable has the same effect as using a + character at the beginning of the command line.  See Instead of Executing the Commands.

Consider the command make -t in the above example.  (The -t option marks targets as up to date without actually running any commands; see Instead of Execution.)  Following the usual definition of -t, a make -t command in the example would create a file named subsystem and do nothing else.  What you really want it to do is run cd subdir; make -t; but that would require executing the command, and -t says not to execute commands.

The special feature makes this do what you want: whenever a command line of a rule contains the variable MAKE, the flags -t, -n and -q do not apply to that line.  Command lines containing MAKE are executed normally despite the presence of a flag that causes most commands not to be run.  The usual MAKEFLAGS mechanism passes the flags to the sub-make (see Communicating Options to a Sub-make), so your request to touch the files, or print the commands, is propagated to the subsystem.

Communicating Variables to a Sub-make
-------------------------------------

Variable values of the top-level make can be passed to the sub-make through the environment by explicit request.  These variables are defined in the sub-make as defaults, but do not override what is specified in the makefile used by the sub-make makefile unless you use the -e switch (see Summary of Options).

To pass down, or export, a variable, make adds the variable and its value to the environment for running each command.  The sub-make, in turn, uses the environment to initialize its table of variable values.  See Variables from the Environment.

Except by explicit request, make exports a variable only if it is either defined in the environment initially or set on the command line, and if its name consists only of letters, numbers, and underscores. Some shells cannot cope with environment variable names consisting of characters other than letters, numbers, and underscores.

The special variables SHELL and MAKEFLAGS are always exported (unless you unexport them). MAKEFILES is exported if you set it to anything.

make automatically passes down variable values that were defined on the command line, by putting them in the MAKEFLAGS variable.